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https://github.com/ARM-software/arm-trusted-firmware.git
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4c700c1563
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
53 lines
1.1 KiB
ArmAsm
53 lines
1.1 KiB
ArmAsm
/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <platform_def.h>
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.global enable_mpu_direct_el2
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/* void enable_mmu_direct_el2(unsigned int flags) */
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func enable_mpu_direct_el2
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#if ENABLE_ASSERTIONS
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mrs x1, sctlr_el2
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tst x1, #SCTLR_M_BIT
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ASM_ASSERT(eq)
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#endif
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mov x7, x0
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adrp x0, mmu_cfg_params
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add x0, x0, :lo12:mmu_cfg_params
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/* (MAIRs are already set up) */
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/* TCR */
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ldr x2, [x0, #(MMU_CFG_TCR << 3)]
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msr tcr_el2, x2
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/*
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* Ensure all translation table writes have drained into memory, the TLB
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* invalidation is complete, and translation register writes are
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* committed before enabling the MMU
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*/
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dsb ish
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isb
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/* Set and clear required fields of SCTLR */
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mrs x4, sctlr_el2
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mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
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orr x4, x4, x5
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/* Additionally, amend SCTLR fields based on flags */
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bic x5, x4, #SCTLR_C_BIT
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tst x7, #DISABLE_DCACHE
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csel x4, x5, x4, ne
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msr sctlr_el2, x4
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isb
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ret
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endfunc enable_mpu_direct_el2
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