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Currently, EL3 context registers are duplicated per-world per-cpu. Some registers have the same value across all CPUs, so this patch moves these registers out into a per-world context to reduce memory usage. Change-Id: I91294e3d5f4af21a58c23599af2bdbd2a747c54a Signed-off-by: Elizabeth Ho <elizabeth.ho@arm.com> Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/*
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* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/cassert.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/sve.h>
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CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long);
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CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short);
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CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule);
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/*
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* Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
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* VECTOR_SIZE = (LEN+1) * 128
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*/
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#define CONVERT_SVE_LENGTH(x) (((x / 128) - 1))
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void sve_enable_per_world(per_world_context_t *per_world_ctx)
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{
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u_register_t cptr_el3;
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/* Enable access to SVE functionality for all ELs. */
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cptr_el3 = per_world_ctx->ctx_cptr_el3;
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cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
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per_world_ctx->ctx_cptr_el3 = cptr_el3;
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/* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */
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per_world_ctx->ctx_zcr_el3 = (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN));
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}
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void sve_init_el2_unused(void)
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{
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/*
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* CPTR_EL2.TFP: Set to zero so that Non-secure accesses to Advanced
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* SIMD and floating-point functionality from both Execution states do
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* not trap to EL2.
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*/
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write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TFP_BIT);
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}
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void sve_disable_per_world(per_world_context_t *per_world_ctx)
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{
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u_register_t reg;
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/* Disable SVE and FPU since they share registers. */
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reg = per_world_ctx->ctx_cptr_el3;
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reg &= ~CPTR_EZ_BIT; /* Trap SVE */
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reg |= TFP_BIT; /* Trap FPU/SIMD */
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per_world_ctx->ctx_cptr_el3 = reg;
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}
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