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33e6aaacf1
This patch disables trapping to EL3 when the FEAT_FGT2 specific trap registers are accessed by setting the SCR_EL3.FGTEn2 bit Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a
27 lines
578 B
C
27 lines
578 B
C
/*
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* Copyright (c) 2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/extensions/fgt2.h>
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void fgt2_enable(cpu_context_t *context)
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{
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u_register_t reg;
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el3_state_t *state;
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state = get_el3state_ctx(context);
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/* Set the FGTEN2 bit in SCR_EL3 to enable access to HFGITR2_EL2,
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* HFGRTR2_EL2, HFGWTR_EL2, HDFGRTR2_EL2, and HDFGWTR2_EL2.
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*/
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reg = read_ctx_reg(state, CTX_SCR_EL3);
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reg |= SCR_FGTEN2_BIT;
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write_ctx_reg(state, CTX_SCR_EL3, reg);
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}
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