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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
178 lines
3.8 KiB
ArmAsm
178 lines
3.8 KiB
ArmAsm
/*
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* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a15.h>
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#include <cpu_macros.S>
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/*
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* Cortex-A15 support LPAE and Virtualization Extensions.
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* Don't care if confiugration uses or not LPAE and VE.
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* Therefore, where we don't check ARCH_IS_ARMV7_WITH_LPAE/VE
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*/
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.macro assert_cache_enabled
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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.endm
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func cortex_a15_disable_smp
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ldcopr r0, ACTLR
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bic r0, #CORTEX_A15_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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#if ERRATA_A15_816470
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/*
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* Invalidate any TLB address
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*/
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mov r0, #0
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stcopr r0, TLBIMVA
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#endif
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dsb sy
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bx lr
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endfunc cortex_a15_disable_smp
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func cortex_a15_enable_smp
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A15_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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bx lr
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endfunc cortex_a15_enable_smp
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A15 Errata #816470.
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* This applies only to revision >= r3p0 of Cortex A15.
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* ----------------------------------------------------
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*/
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func check_errata_816470
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/*
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* Even though this is only needed for revision >= r3p0, it is always
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* applied because of the low cost of the workaround.
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*/
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mov r0, #ERRATA_APPLIES
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bx lr
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endfunc check_errata_816470
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add_erratum_entry cortex_a15, ERRATUM(816470), ERRATA_A15_816470
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A15 Errata #827671.
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* This applies only to revision >= r3p0 of Cortex A15.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ----------------------------------------------------
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*/
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func errata_a15_827671_wa
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/*
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* Compare r0 against revision r3p0
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*/
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mov r2, lr
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bl check_errata_827671
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr r0, CORTEX_A15_ACTLR2
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orr r0, #CORTEX_A15_ACTLR2_INV_DCC_BIT
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stcopr r0, CORTEX_A15_ACTLR2
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isb
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1:
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bx r2
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endfunc errata_a15_827671_wa
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func check_errata_827671
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mov r1, #0x30
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b cpu_rev_var_hs
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endfunc check_errata_827671
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add_erratum_entry cortex_a15, ERRATUM(827671), ERRATA_A15_827671
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func check_errata_cve_2017_5715
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#if WORKAROUND_CVE_2017_5715
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mov r0, #ERRATA_APPLIES
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#else
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mov r0, #ERRATA_MISSING
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#endif
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bx lr
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endfunc check_errata_cve_2017_5715
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add_erratum_entry cortex_a15, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov r0, #ERRATA_APPLIES
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#else
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mov r0, #ERRATA_MISSING
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#endif
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bx lr
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endfunc check_errata_cve_2022_23960
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add_erratum_entry cortex_a15, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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func cortex_a15_reset_func
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mov r5, lr
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bl cpu_get_rev_var
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#if ERRATA_A15_827671
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bl errata_a15_827671_wa
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#endif
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#if IMAGE_BL32 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A15_ACTLR_INV_BTB_BIT
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stcopr r0, ACTLR
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ldr r0, =wa_cve_2017_5715_icache_inv_vbar
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stcopr r0, VBAR
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stcopr r0, MVBAR
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/* isb will be applied in the course of the reset func */
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#endif
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mov lr, r5
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b cortex_a15_enable_smp
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endfunc cortex_a15_reset_func
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func cortex_a15_core_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 cache */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a15_disable_smp
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endfunc cortex_a15_core_pwr_dwn
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func cortex_a15_cluster_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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bl plat_disable_acp
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/* Flush L2 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a15_disable_smp
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endfunc cortex_a15_cluster_pwr_dwn
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declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \
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cortex_a15_reset_func, \
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cortex_a15_core_pwr_dwn, \
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cortex_a15_cluster_pwr_dwn
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