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375f538a79
This patch adds the TSPD service which is responsible for managing communication between the non-secure state and the Test Secure Payload (TSP) executing in S-EL1. The TSPD does the following: 1. Determines the location of the TSP (BL3-2) image and passes control to it for initialization. This is done by exporting the 'bl32_init()' function. 2. Receives a structure containing the various entry points into the TSP image as a response to being initialized. The TSPD uses this information to determine how the TSP should be entered depending on the type of operation. 3. Implements a synchronous mechanism for entering into and returning from the TSP image. This mechanism saves the current C runtime context on top of the current stack and jumps to the TSP through an ERET instruction. The TSP issues an SMC to indicate completion of the previous request. The TSPD restores the saved C runtime context and resumes TSP execution. This patch also introduces a Make variable 'SPD' to choose the specific SPD to include in the build. By default, no SPDs are included in the build. Change-Id: I124da5695cdc510999b859a1bf007f4d049e04f3 Co-authored-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
134 lines
5.8 KiB
C
134 lines
5.8 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SPD_PRIVATE_H__
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#define __SPD_PRIVATE_H__
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#include <context.h>
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#include <arch.h>
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#include <psci.h>
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#include <tsp.h>
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/*******************************************************************************
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* Secure Payload PM state information e.g. SP is suspended, uninitialised etc
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******************************************************************************/
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#define TSP_STATE_OFF 0
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#define TSP_STATE_ON 1
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#define TSP_STATE_SUSPEND 2
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/*******************************************************************************
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* Secure Payload execution state information i.e. aarch32 or aarch64
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******************************************************************************/
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#define TSP_AARCH32 MODE_RW_32
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#define TSP_AARCH64 MODE_RW_64
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/*******************************************************************************
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* The SPD should know the type of Secure Payload.
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******************************************************************************/
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#define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP
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#define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP
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#define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP
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/*******************************************************************************
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* Secure Payload migrate type information as known to the SPD. We assume that
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* the SPD is dealing with an MP Secure Payload.
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******************************************************************************/
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#define TSP_MIGRATE_INFO TSP_TYPE_MP
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/*******************************************************************************
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* Number of cpus that the present on this platform. TODO: Rely on a topology
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* tree to determine this in the future to avoid assumptions about mpidr
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* allocation
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******************************************************************************/
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#define TSPD_CORE_COUNT PLATFORM_CORE_COUNT
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/*******************************************************************************
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* Constants that allow assembler code to preserve callee-saved registers of the
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* C runtime context while performing a security state switch.
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******************************************************************************/
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#define TSPD_C_RT_CTX_X19 0x0
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#define TSPD_C_RT_CTX_X20 0x8
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#define TSPD_C_RT_CTX_X21 0x10
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#define TSPD_C_RT_CTX_X22 0x18
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#define TSPD_C_RT_CTX_X23 0x20
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#define TSPD_C_RT_CTX_X24 0x28
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#define TSPD_C_RT_CTX_X25 0x30
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#define TSPD_C_RT_CTX_X26 0x38
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#define TSPD_C_RT_CTX_X27 0x40
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#define TSPD_C_RT_CTX_X28 0x48
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#define TSPD_C_RT_CTX_X29 0x50
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#define TSPD_C_RT_CTX_X30 0x58
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#define TSPD_C_RT_CTX_SIZE 0x60
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#define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT)
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#ifndef __ASSEMBLY__
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/* AArch64 callee saved general purpose register context structure. */
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DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES);
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/*
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* Compile time assertion to ensure that both the compiler and linker
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* have the same double word aligned view of the size of the C runtime
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* register context.
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*/
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CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs), \
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assert_spd_c_rt_regs_size_mismatch);
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/*******************************************************************************
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* Structure which helps the SPD to maintain the per-cpu state of the SP.
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* 'state' - collection of flags to track SP state e.g. on/off
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* 'mpidr' - mpidr to associate a context with a cpu
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* 'c_rt_ctx' - stack address to restore C runtime context from after returning
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* from a synchronous entry into the SP.
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* 'cpu_ctx' - space to maintain SP architectural state
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******************************************************************************/
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typedef struct {
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uint32_t state;
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uint64_t mpidr;
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uint64_t c_rt_ctx;
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cpu_context cpu_ctx;
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} tsp_context;
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/*******************************************************************************
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* Function & Data prototypes
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******************************************************************************/
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extern uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
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extern void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
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extern uint64_t tspd_synchronous_sp_entry(tsp_context *tsp_ctx);
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extern void __dead2 tspd_synchronous_sp_exit(tsp_context *tsp_ctx, uint64_t ret);
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extern int32_t tspd_init_secure_context(uint64_t entrypoint,
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uint32_t rw,
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uint64_t mpidr,
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tsp_context *tsp_ctx);
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extern tsp_context tspd_sp_context[TSPD_CORE_COUNT];
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extern entry_info *tsp_entry_info;
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#endif /*__ASSEMBLY__*/
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#endif /* __SPD_PRIVATE_H__ */
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