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c9f352c362
The model has a bug where it will not clear CPUPWRCTLR_EL1 on reset, even though the actual cores do. The write of 1 to the bit itself triggers the powerdown sequnece, regardless of the value before the write. As such, the bug does not impact functionality but it does throw off software reading it. Clear the bit on Travis and Gelas as they are the only ones to require reading it back. Change-Id: I765a7fa055733d522480be30d412e3b417af2bd7 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
67 lines
1.8 KiB
ArmAsm
67 lines
1.8 KiB
ArmAsm
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <travis.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Travis must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Travis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if FEAT_PABANDON == 0
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#error "Travis must be compiled with FEAT_PABANDON enabled"
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#endif
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#if ERRATA_SME_POWER_DOWN == 0
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#error "Travis needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly"
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#endif
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cpu_reset_func_start travis
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/* ----------------------------------------------------
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* Disable speculative loads
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* ----------------------------------------------------
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*/
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msr SSBS, xzr
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/* model bug: not cleared on reset */
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sysreg_bit_clear TRAVIS_IMP_CPUPWRCTLR_EL1, \
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TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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cpu_reset_func_end travis
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func travis_core_pwr_dwn
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/* ---------------------------------------------------
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* Flip CPU power down bit in power control register.
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* It will be set on powerdown and cleared on wakeup
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* ---------------------------------------------------
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*/
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sysreg_bit_toggle TRAVIS_IMP_CPUPWRCTLR_EL1, \
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TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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isb
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ret
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endfunc travis_core_pwr_dwn
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.section .rodata.travis_regs, "aS"
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travis_regs: /* The ASCII list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func travis_cpu_reg_dump
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adr x6, travis_regs
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mrs x8, TRAVIS_IMP_CPUECTLR_EL1
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ret
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endfunc travis_cpu_reg_dump
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declare_cpu_ops travis, TRAVIS_MIDR, \
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travis_reset_func, \
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travis_core_pwr_dwn
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