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https://github.com/ARM-software/arm-trusted-firmware.git
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367d0ffb14
This patch modifies GICv3 and TZC drivers to add AArch32 support. No modifications are required for the GICv2 driver for AArch32 support. The TZC driver assumes that the secure world is running in Little-Endian mode to do 64 bit manipulations. Assertions are present to validate the assumption. Note: The legacy GICv3 driver is not supported for AArch32. Change-Id: Id1bc75a9f5dafb9715c9500ca77b4606eb1e2458
235 lines
7.8 KiB
C
235 lines
7.8 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <mmio.h>
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#include <tzc_common.h>
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#define DEFINE_TZC_COMMON_WRITE_ACTION(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_action( \
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uintptr_t base, \
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tzc_action_t action) \
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{ \
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mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \
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action); \
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}
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#define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_region_base( \
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uintptr_t base, \
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int region_no, \
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unsigned long long region_base) \
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{ \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \
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(uint32_t)region_base); \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \
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(uint32_t)(region_base >> 32)); \
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}
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#define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_region_top( \
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uintptr_t base, \
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int region_no, \
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unsigned long long region_top) \
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{ \
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mmio_write_32(base + \
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TZC_REGION_OFFSET \
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(TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \
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(uint32_t)region_top); \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \
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(uint32_t)(region_top >> 32)); \
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}
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#define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_region_attributes( \
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uintptr_t base, \
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int region_no, \
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unsigned int attr) \
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{ \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_ATTR_0_OFFSET, \
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attr); \
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}
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#define DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_region_id_access( \
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uintptr_t base, \
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int region_no, \
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unsigned int val) \
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{ \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \
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val); \
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}
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/*
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* It is used to program region 0 ATTRIBUTES and ACCESS register.
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*/
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#define DEFINE_TZC_COMMON_CONFIGURE_REGION0(fn_name) \
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void _tzc##fn_name##_configure_region0(uintptr_t base, \
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tzc_region_attributes_t sec_attr, \
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unsigned int ns_device_access) \
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{ \
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assert(base); \
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VERBOSE("TrustZone : Configuring region 0 " \
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"(TZC Interface Base=%p sec_attr=0x%x," \
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" ns_devs=0x%x)\n", (void *)base, \
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sec_attr, ns_device_access); \
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\
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/* Set secure attributes on region 0 */ \
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_tzc##fn_name##_write_region_attributes(base, 0, \
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sec_attr << TZC_REGION_ATTR_SEC_SHIFT); \
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\
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/***************************************************/ \
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/* Specify which non-secure devices have permission*/ \
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/* to access region 0. */ \
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/***************************************************/ \
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_tzc##fn_name##_write_region_id_access(base, \
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0, \
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ns_device_access); \
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}
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/*
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* It is used to program a region from 1 to 8 in the TrustZone controller.
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* NOTE:
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* Region 0 is special; it is preferable to use
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* ##fn_name##_configure_region0 for this region (see comment for
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* that function).
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*/
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#define DEFINE_TZC_COMMON_CONFIGURE_REGION(fn_name) \
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void _tzc##fn_name##_configure_region(uintptr_t base, \
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unsigned int filters, \
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int region_no, \
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unsigned long long region_base, \
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unsigned long long region_top, \
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tzc_region_attributes_t sec_attr, \
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unsigned int nsaid_permissions) \
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{ \
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assert(base); \
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VERBOSE("TrustZone : Configuring region " \
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"(TZC Interface Base: %p, region_no = %d)" \
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"...\n", (void *)base, region_no); \
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VERBOSE("TrustZone : ... base = %llx, top = %llx," \
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"\n", region_base, region_top);\
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VERBOSE("TrustZone : ... sec_attr = 0x%x," \
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" ns_devs = 0x%x)\n", \
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sec_attr, nsaid_permissions); \
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\
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/***************************************************/ \
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/* Inputs look ok, start programming registers. */ \
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/* All the address registers are 32 bits wide and */ \
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/* have a LOW and HIGH */ \
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/* component used to construct an address up to a */ \
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/* 64bit. */ \
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/***************************************************/ \
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_tzc##fn_name##_write_region_base(base, \
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region_no, region_base); \
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_tzc##fn_name##_write_region_top(base, \
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region_no, region_top); \
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\
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/* Enable filter to the region and set secure attributes */\
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_tzc##fn_name##_write_region_attributes(base, \
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region_no, \
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(sec_attr << TZC_REGION_ATTR_SEC_SHIFT) |\
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(filters << TZC_REGION_ATTR_F_EN_SHIFT));\
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\
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/***************************************************/ \
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/* Specify which non-secure devices have permission*/ \
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/* to access this region. */ \
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/***************************************************/ \
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_tzc##fn_name##_write_region_id_access(base, \
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region_no, \
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nsaid_permissions); \
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}
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#if DEBUG
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static unsigned int _tzc_read_peripheral_id(uintptr_t base)
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{
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unsigned int id;
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id = mmio_read_32(base + PID0_OFF);
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/* Masks DESC part in PID1 */
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id |= ((mmio_read_32(base + PID1_OFF) & 0xF) << 8);
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return id;
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}
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#ifdef AARCH32
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static unsigned long long _tzc_get_max_top_addr(int addr_width)
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{
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/*
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* Assume at least 32 bit wide address and initialize the max.
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* This function doesn't use 64-bit integer arithmetic to avoid
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* having to implement additional compiler library functions.
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*/
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unsigned long long addr_mask = 0xFFFFFFFF;
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uint32_t *addr_ptr = (uint32_t *)&addr_mask;
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assert(addr_width >= 32);
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/* This logic works only on little - endian platforms */
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assert((read_sctlr() & SCTLR_EE_BIT) == 0);
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/*
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* If required address width is greater than 32, populate the higher
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* 32 bits of the 64 bit field with the max address.
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*/
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if (addr_width > 32)
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*(addr_ptr + 1) = ((1 << (addr_width - 32)) - 1);
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return addr_mask;
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}
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#else
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#define _tzc_get_max_top_addr(addr_width)\
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(UINT64_MAX >> (64 - (addr_width)))
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#endif /* AARCH32 */
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#endif
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