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b42ceebb40
The watchdog block on the IMX is mercifully simple. This patch maps the various registers and bits associated with the block. We are mostly only really interested in the power-down-enable (PDE) bits in the block for the purposes of ATF. The i.MX7 Solo Applications Processor Reference Manual details the PDE bit as follows: "Power Down Enable bit. Reset value of this bit is 1, which means the power down counter inside the WDOG is enabled after reset. The software must write 0 to this bit to disable the counter within 16 seconds of reset de-assertion. Once disabled this counter cannot be enabled again. See Power-down counter event for operation of this counter." This patch does that zero write in-lieu of later phases in the boot no-longer have the necessary permissions to rewrite the PDE bit directly. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
24 lines
507 B
C
24 lines
507 B
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <mmio.h>
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#include <imx_regs.h>
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#include <imx_wdog.h>
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static void imx_wdog_power_down(unsigned long base)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)base;
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mmio_write_16((uintptr_t)&wdog->wmcr, 0);
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}
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void imx_wdog_init(void)
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{
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imx_wdog_power_down(WDOG1_BASE);
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imx_wdog_power_down(WDOG2_BASE);
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imx_wdog_power_down(WDOG3_BASE);
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imx_wdog_power_down(WDOG4_BASE);
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}
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