mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 10:04:26 +00:00
35e98e5588
Make codebase consistent in its use of #include "" syntax for user includes and #include <> syntax for system includes. Fixes ARM-software/tf-issues#65 Change-Id: If2f7c4885173b1fd05ac2cde5f1c8a07000c7a33
406 lines
14 KiB
C
406 lines
14 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_H__
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#define __PLATFORM_H__
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#include <arch.h>
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#include <mmio.h>
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#include <psci.h>
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#include <bl_common.h>
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#include <io_storage.h>
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x800
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/* Size of coherent stacks for debug and release builds */
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#if DEBUG
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#define PCPU_DV_MEM_STACK_SIZE 0x400
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#else
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#define PCPU_DV_MEM_STACK_SIZE 0x300
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#endif
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#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
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/* Trusted Boot Firmware BL2 */
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#define BL2_IMAGE_NAME "bl2.bin"
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/* EL3 Runtime Firmware BL31 */
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#define BL31_IMAGE_NAME "bl31.bin"
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/* Secure Payload BL32 (Trusted OS) */
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#define BL32_IMAGE_NAME "bl32.bin"
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/* Non-Trusted Firmware BL33 and its load address */
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#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
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#define NS_IMAGE_OFFSET (DRAM_BASE + 0x8000000) /* DRAM + 128MB */
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/* Firmware Image Package */
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#define FIP_IMAGE_NAME "fip.bin"
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT 2ull
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER1_CORE_COUNT 4
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define PRIMARY_CPU 0x0
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* Constants for accessing platform configuration */
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#define CONFIG_GICD_ADDR 0
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#define CONFIG_GICC_ADDR 1
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#define CONFIG_GICH_ADDR 2
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#define CONFIG_GICV_ADDR 3
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#define CONFIG_MAX_AFF0 4
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#define CONFIG_MAX_AFF1 5
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/* Indicate whether the CPUECTLR SMP bit should be enabled. */
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#define CONFIG_CPU_SETUP 6
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#define CONFIG_BASE_MMAP 7
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/* Indicates whether CCI should be enabled on the platform. */
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#define CONFIG_HAS_CCI 8
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#define CONFIG_HAS_TZC 9
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#define CONFIG_LIMIT 10
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define TZROM_BASE 0x00000000
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#define TZROM_SIZE 0x04000000
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#define TZRAM_BASE 0x04000000
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#define TZRAM_SIZE 0x40000
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#define FLASH0_BASE 0x08000000
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#define FLASH0_SIZE TZROM_SIZE
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#define FLASH1_BASE 0x0c000000
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#define FLASH1_SIZE 0x04000000
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#define PSRAM_BASE 0x14000000
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#define PSRAM_SIZE 0x04000000
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#define VRAM_BASE 0x18000000
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#define VRAM_SIZE 0x02000000
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE 0x1a000000
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#define DEVICE0_SIZE 0x12200000
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#define DEVICE1_BASE 0x2f000000
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#define DEVICE1_SIZE 0x200000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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/* Location of trusted dram on the base fvp */
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#define TZDRAM_BASE 0x06000000
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#define TZDRAM_SIZE 0x02000000
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#define MBOX_OFF 0x1000
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#define DRAM_BASE 0x80000000ull
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#define DRAM_SIZE 0x80000000ull
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#define PCIE_EXP_BASE 0x40000000
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#define TZRNG_BASE 0x7fe60000
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#define TZNVCTR_BASE 0x7fe70000
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#define TZROOTKEY_BASE 0x7fe80000
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/* Memory mapped Generic timer interfaces */
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#define SYS_CNTCTL_BASE 0x2a430000
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#define SYS_CNTREAD_BASE 0x2a800000
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#define SYS_TIMCTL_BASE 0x2a810000
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/* Counter timer module offsets */
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#define CNTNSAR 0x4
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#define CNTNSAR_NS_SHIFT(x) x
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#define CNTACR_BASE(x) (0x40 + (x << 2))
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#define CNTACR_RPCT_SHIFT 0x0
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#define CNTACR_RVCT_SHIFT 0x1
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#define CNTACR_RFRQ_SHIFT 0x2
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#define CNTACR_RVOFF_SHIFT 0x3
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#define CNTACR_RWVT_SHIFT 0x4
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#define CNTACR_RWPT_SHIFT 0x5
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/* V2M motherboard system registers & offsets */
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#define VE_SYSREGS_BASE 0x1c010000
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#define V2M_SYS_ID 0x0
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#define V2M_SYS_LED 0x8
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#define V2M_SYS_CFGDATA 0xa0
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#define V2M_SYS_CFGCTRL 0xa4
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/*
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* V2M sysled bit definitions. The values written to this
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* register are defined in arch.h & runtime_svc.h. Only
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* used by the primary cpu to diagnose any cold boot issues.
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*
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* SYS_LED[0] - Security state (S=0/NS=1)
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* SYS_LED[2:1] - Exception Level (EL3-EL0)
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* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
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*
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*/
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#define SYS_LED_SS_SHIFT 0x0
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#define SYS_LED_EL_SHIFT 0x1
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#define SYS_LED_EC_SHIFT 0x3
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#define SYS_LED_SS_MASK 0x1
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#define SYS_LED_EL_MASK 0x3
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#define SYS_LED_EC_MASK 0x1f
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/* V2M sysid register bits */
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#define SYS_ID_REV_SHIFT 27
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#define SYS_ID_HBI_SHIFT 16
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#define SYS_ID_BLD_SHIFT 12
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#define SYS_ID_ARCH_SHIFT 8
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#define SYS_ID_FPGA_SHIFT 0
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#define SYS_ID_REV_MASK 0xf
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#define SYS_ID_HBI_MASK 0xfff
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#define SYS_ID_BLD_MASK 0xf
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#define SYS_ID_ARCH_MASK 0xf
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#define SYS_ID_FPGA_MASK 0xff
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#define SYS_ID_BLD_LENGTH 4
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#define REV_FVP 0x0
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#define HBI_FVP_BASE 0x020
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#define HBI_FOUNDATION 0x010
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#define BLD_GIC_VE_MMAP 0x0
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#define BLD_GIC_A53A57_MMAP 0x1
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#define ARCH_MODEL 0x1
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/* FVP Power controller base address*/
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#define PWRC_BASE 0x1c100000
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/*******************************************************************************
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* Platform specific per affinity states. Distinction between off and suspend
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* is made to allow reporting of a suspended cpu as still being on e.g. in the
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* affinity_info psci call.
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******************************************************************************/
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#define PLATFORM_MAX_AFF0 4
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#define PLATFORM_MAX_AFF1 2
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#define PLAT_AFF_UNK 0xff
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#define PLAT_AFF0_OFF 0x0
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#define PLAT_AFF0_ONPENDING 0x1
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#define PLAT_AFF0_SUSPEND 0x2
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#define PLAT_AFF0_ON 0x3
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#define PLAT_AFF1_OFF 0x0
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#define PLAT_AFF1_ONPENDING 0x1
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#define PLAT_AFF1_SUSPEND 0x2
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#define PLAT_AFF1_ON 0x3
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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#define BL2_BASE 0x0402D000
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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#define BL31_BASE 0x0400C000
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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#define BL32_BASE (TZDRAM_BASE + 0x2000)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 3
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define CCI400_BASE 0x2c090000
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#define CCI400_SL_IFACE_CLUSTER0 3
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#define CCI400_SL_IFACE_CLUSTER1 4
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#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
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CCI400_SL_IFACE_CLUSTER1 : \
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CCI400_SL_IFACE_CLUSTER0)
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* VE compatible GIC memory map */
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#define VE_GICD_BASE 0x2c001000
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#define VE_GICC_BASE 0x2c002000
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#define VE_GICH_BASE 0x2c004000
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#define VE_GICV_BASE 0x2c006000
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/* Base FVP compatible GIC memory map */
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#define BASE_GICD_BASE 0x2f000000
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#define BASE_GICR_BASE 0x2f100000
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#define BASE_GICC_BASE 0x2c000000
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#define BASE_GICH_BASE 0x2c010000
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#define BASE_GICV_BASE 0x2c02f000
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#define IRQ_TZ_WDOG 56
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#define IRQ_SEC_PHY_TIMER 29
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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#define IRQ_SEC_SGI_2 10
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#define IRQ_SEC_SGI_3 11
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#define IRQ_SEC_SGI_4 12
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#define IRQ_SEC_SGI_5 13
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#define IRQ_SEC_SGI_6 14
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#define IRQ_SEC_SGI_7 15
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#define IRQ_SEC_SGI_8 16
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/*******************************************************************************
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* PL011 related constants
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******************************************************************************/
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#define PL011_UART0_BASE 0x1c090000
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#define PL011_UART1_BASE 0x1c0a0000
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#define PL011_UART2_BASE 0x1c0b0000
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#define PL011_UART3_BASE 0x1c0c0000
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#define PL011_BASE PL011_UART0_BASE
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/*******************************************************************************
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* TrustZone address space controller related constants
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******************************************************************************/
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#define TZC400_BASE 0x2a4a0000
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/*
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* The NSAIDs for this platform as used to program the TZC400.
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* TODO:
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* This list and the numbers in it is still changing on the Base FVP.
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* For now only specify the NSAIDs we actually use.
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*/
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/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */
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#define FVP_AID_WIDTH 4
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#define FVP_NSAID_DEFAULT 0
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#define FVP_NSAID_AP 9 /* Application Processors */
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/* FIXME: Currently incorrectly used by Virtio */
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#define FVP_NSAID_RES5 15
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#ifndef __ASSEMBLY__
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typedef volatile struct {
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unsigned long value
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__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
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} mailbox;
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/*******************************************************************************
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* Function and variable prototypes
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******************************************************************************/
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extern unsigned long *bl1_normal_ram_base;
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extern unsigned long *bl1_normal_ram_len;
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extern unsigned long *bl1_normal_ram_limit;
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extern unsigned long *bl1_normal_ram_zi_base;
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extern unsigned long *bl1_normal_ram_zi_len;
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extern unsigned long *bl1_coherent_ram_base;
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extern unsigned long *bl1_coherent_ram_len;
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extern unsigned long *bl1_coherent_ram_limit;
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extern unsigned long *bl1_coherent_ram_zi_base;
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extern unsigned long *bl1_coherent_ram_zi_len;
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extern unsigned long warm_boot_entrypoint;
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extern void bl1_plat_arch_setup(void);
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extern void bl2_plat_arch_setup(void);
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extern void bl31_plat_arch_setup(void);
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extern int platform_setup_pm(plat_pm_ops **);
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extern unsigned int platform_get_core_pos(unsigned long mpidr);
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extern void disable_mmu(void);
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extern void enable_mmu(void);
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extern void configure_mmu(meminfo *,
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unsigned long,
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unsigned long,
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unsigned long,
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unsigned long);
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extern unsigned long platform_get_cfgvar(unsigned int);
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extern int platform_config_setup(void);
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extern void plat_report_exception(unsigned long);
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extern unsigned long plat_get_ns_image_entrypoint(void);
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extern unsigned long platform_get_stack(unsigned long mpidr);
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extern uint64_t plat_get_syscnt_freq(void);
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/* Declarations for fvp_gic.c */
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extern void gic_cpuif_deactivate(unsigned int);
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extern void gic_cpuif_setup(unsigned int);
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extern void gic_pcpu_distif_setup(unsigned int);
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extern void gic_setup(void);
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/* Declarations for fvp_topology.c */
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extern int plat_setup_topology(void);
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extern int plat_get_max_afflvl(void);
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extern unsigned int plat_get_aff_count(unsigned int, unsigned long);
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extern unsigned int plat_get_aff_state(unsigned int, unsigned long);
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/* Declarations for plat_io_storage.c */
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extern void io_setup(void);
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extern int plat_get_image_source(const char *image_name,
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io_dev_handle *dev_handle, void **image_spec);
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/* Declarations for plat_security.c */
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extern void plat_security_setup(void);
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#endif /*__ASSEMBLY__*/
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#endif /* __PLATFORM_H__ */
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