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79629b1a79
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
786 lines
26 KiB
C
786 lines
26 KiB
C
/*
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* Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DDRPHY_PHYINIT_STRUCT_H
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#define DDRPHY_PHYINIT_STRUCT_H
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/* This file defines the internal data structures used in PhyInit to store user configuration */
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/* DIMM Type definitions */
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#define DDR_DIMMTYPE_NODIMM 4U /* No DIMM (Soldered-on) */
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/*
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* Structure for basic user inputs
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*
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* The following basic data structure must be set and completed correctly so
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* that the PhyInit software package can accurate program PHY registers.
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*/
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struct user_input_basic {
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uint32_t dramtype; /*
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* DRAM module type.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | DDR4
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* 0x1 | DDR3
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* 0x2 | LPDDR4
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*/
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uint32_t dimmtype; /*
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* DIMM type.
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*
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* Value | Description
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* ----- | ------
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* 0x4 | No DIMM (Soldered-on) (DDR_DIMMTYPE_NODIMM)
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*/
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uint32_t lp4xmode; /*
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* LPDDR4X mode support.
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* Only used for LPDDR4, but not valid here.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | LPDDR4 mode, when dramtype is LPDDR4
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*/
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uint32_t numdbyte; /* Number of dbytes physically instantiated */
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uint32_t numactivedbytedfi0; /* Number of active dbytes to be controlled by dfi0 */
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uint32_t numactivedbytedfi1; /*
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* Number of active dbytes to be controlled by dfi1.
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* Only used for LPDDR4.
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*/
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uint32_t numanib; /* Number of ANIBs physically instantiated */
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uint32_t numrank_dfi0; /* Number of ranks in DFI0 channel */
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uint32_t numrank_dfi1; /* Number of ranks in DFI1 channel (if DFI1 exists) */
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uint32_t dramdatawidth; /*
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* Width of the DRAM device.
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*
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* Enter 4,8,16 or 32 depending on protocol and dram type
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* according below table.
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*
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* Protocol | Valid Options | Default
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* -------- | ------------- | ---
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* DDR3 | 4,8,16 | 8
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* DDR4 | 4,8,16 | 8
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* LPDDR4 | 8,16 | 16
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*
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* For mixed x8 and x16 width devices, set variable to x8.
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*/
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uint32_t numpstates; /* Number of p-states used. Must be set to 1 */
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uint32_t frequency; /*
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* Memclk frequency for each PState.
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* Memclk frequency in MHz round up to next highest integer.
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* Enter 334 for 333.333, etc.
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*/
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uint32_t pllbypass; /*
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* Indicates if PLL should be in Bypass mode.
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* If DDR datarate < 333, PLL must be in Bypass Mode.
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*
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* Value | Description
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* ----- | ------
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* 0x1 | Enabled
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* 0x0 | Disabled
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*/
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uint32_t dfifreqratio; /*
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* Selected Dfi Frequency ratio.
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* Used to program the dfifreqratio register. This register
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* controls how dfi_freq_ratio input pin should be driven
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* inaccordance with DFI Spec.
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*
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* Binary Value | Description
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* ----- | ------
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* 2'b01 | 1:2 DFI Frequency Ratio (default)
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*/
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uint32_t dfi1exists; /* Indicates if the PHY configuration has Dfi1 channel */
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uint32_t train2d; /* Obsolete. Not used. */
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uint32_t hardmacrover; /*
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* Hard Macro Family version in use.
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*
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* Value | Description
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* ----- | ------
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* 3 | hardmacro family D
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*/
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uint32_t readdbienable; /* Obsolete. Not Used. */
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uint32_t dfimode; /* Obsolete. Not Used. */
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};
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/*
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* Structure for advanced user inputs
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*/
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struct user_input_advanced {
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uint32_t lp4rxpreamblemode; /*
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* Selects between DRAM read static vs toggle preamble.
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* Determine desired DRAM Read Preamble Mode based on SI
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* Analysis and DRAM Part in use.
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* The PHY training firmware will program DRAM mr1-OP[3]
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* after training based on setting.
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*
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* Value | Description
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* ----- | ------
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* 0x1 | toggling preamble
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* 0x0 | static preamble
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*/
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uint32_t lp4postambleext; /*
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* Extend write postamble in LPDDR4.
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* Only used for LPDDR4.
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* This variable is used to calculate LPDDR4 mr3-OP[1] set
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* in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* Set value according to your SI analysis and DRAM
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* requirement.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | half Memclk postamble
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* 0x1 | 1.5 Memclk postabmle (default)
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*/
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uint32_t d4rxpreamblelength; /*
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* Length of read preamble in DDR4 mode.
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* Only used for DDR4.
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* This variable is used to calculate DDR4 mr4-OP[11] set
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* in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* Set value according to your SI analysis and DRAM
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* requirement.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | 1 Tck
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* 0x1 | 2 Tck (default)
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*/
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uint32_t d4txpreamblelength; /*
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* Length of write preamble in DDR4 mode.
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* Only used for DDR4.
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* This variable is used to calculate DDR4 mr4-OP[12] set
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* in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* Set value according to your SI analysis and DRAM
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* requirement.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | 1 Tck (default)
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* 0x1 | 2 Tck
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*/
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uint32_t extcalresval; /*
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* External Impedance calibration pull-down resistor value
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* select.
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* Indicates value of impedance calibration pull-down
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* resistor connected to BP_ZN pin of the PHY.
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* Value | Description
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* ----- | ------
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* 0x0 | 240 ohm (default)
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*/
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uint32_t is2ttiming; /*
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* Set to 1 to use 2T timing for address/command, otherwise
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* 1T timing will be used.
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* Determine 1T or 2T Timing operation mode based on SI
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* Analysis and DRAM Timing.
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* - In 1T mode, CK, CS, CA all have the same nominal
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* timing, ie. ATxDly[6:0] will have same value for all
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* ANIBs.
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* - In 2T mode, CK, CS,have the same nominal timing
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* (e.g. AtxDly[6:0]=0x00), while CA is delayed by 1UI
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* (e.g. ATxDly[6:0]=0x40)
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* Used to program phycfg setting in messageBlock.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | 1T Timing (default)
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* 0x1 | 2T Timing
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*/
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uint32_t odtimpedance; /*
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* ODT impedance in ohm.
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* Used for programming TxOdtDrvStren registers.
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* Enter 0 for open/high-impedance.
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* Default value: 60
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*/
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uint32_t tximpedance; /*
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* Tx Drive Impedance for DQ/DQS in ohm.
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* Used for programming TxImpedanceCtrl1 registers.
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* Enter 0 for open/high-impedance.
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* Default value: 60
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*/
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uint32_t atximpedance; /*
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* Tx Drive Impedance for AC in ohm.
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* Used for programming ATxImpedance register.
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* Enter 0 for open/high-impedance
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* Default value: 20 (HMA,HMB,HMC,HMD), 40 (HME)
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*/
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uint32_t memalerten; /*
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* Enables BP_ALERT programming of PHY registers.
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* Only used for DDR3 and DDR4.
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* Used for programming MemAlertControl and MemAlertControl2
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* registers.
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* Program if you require using BP_ALERT pin (to receive or
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* terminate signal) of the PHY otherwise leave at default
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* value to save power.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | Disable BP_ALERT (default)
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*/
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uint32_t memalertpuimp; /*
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* Specify MemAlert Pull-up Termination Impedance.
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* Programs the pull-up termination on BP_ALERT.
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* Not valid here (fixed 0 value).
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*/
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uint32_t memalertvreflevel; /*
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* Specify the Vref level for BP_ALERT(MemAlert) Receiver.
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* Not valid here (fixed 0 value).
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*/
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uint32_t memalertsyncbypass; /*
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* When set, this bit bypasses the DfiClk synchronizer on
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* dfi_alert_n.
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* Not valid here (fixed 0 value).
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*/
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uint32_t disdynadrtri; /*
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* Disable Dynamic Per-MEMCLK Address Tristate feature.
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* Program this variable if you require to disable this
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* feature.
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* - In DDR3/2T and DDR4/2T/2N modes, the dynamic tristate
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* feature should be disabled if the controller cannot
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* follow the 2T PHY tristate protocol.
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* - In LPDDR4 mode, the dynamic tristate feature should
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* be disabled.
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*
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* Value | Description
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* ----- | ------
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* 0x1 | Disable Dynamic Tristate
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*/
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uint32_t phymstrtraininterval; /*
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* Specifies the how frequent dfi_phymstr_req is issued by
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* PHY.
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* Only required in LPDDR4.
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* Based on SI analysis determine how frequent DRAM drift
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* compensation and re-training is required.
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* Determine if Memory controller supports DFI PHY Master
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* Interface.
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* Program based on desired setting for
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* PPTTrainSetup.PhyMstrTrainInterval register.
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* Default value: 0xa
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*
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* Example:
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* Value | Description
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* ----- | ------
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* 0xa | PPT Train Interval = 268435456 MEMCLKs (default)
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*/
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uint32_t phymstrmaxreqtoack; /*
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* Max time from dfi_phymstr_req asserted to dfi_phymstr_ack
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* asserted.
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* Only required in LPDDR4.
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* Based on your Memory controller's(MC) specification
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* determine how long the PHY should wait for the assertion
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* of dfi_phymstr_ack once dfi_phymstr_req has been issued
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* by the PHY. If the MC does not ack the PHY's request, PHY
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* may issue dfi_error.
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* This value will be used to program
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* PPTTrainSetup.PhyMstrMaxReqToAck register.
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* Default value: 0x5
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*
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* Example:
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* Value | Description
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* ----- | ------
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* 0x5 | PPT Max. Req to Ack. = 8192 MEMCLKs (default)
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*/
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uint32_t wdqsext; /*
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* Enable Write DQS Extension feature of PHY.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | Disable Write DQS Extension feature. (default)
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* 0x1 | Enable Write DQS Extension feature.
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*/
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uint32_t calinterval; /*
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* Specifies the interval between successive calibrations,
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* in mS.
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* Program variable based on desired setting for
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* CalRate.CalInterval register.
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* - Fixed 0x9 value (20mS interval)
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*/
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uint32_t calonce; /*
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* This setting changes the behaviour of CalRun register.
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* If you desire to manually trigger impedance calibration
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* in mission mode set this variable to 1, and toggle CalRun
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* in mission mode.
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*
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* Value | Description
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* ----- | ------
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* 0x0 | Calibration will proceed at the rate determined
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* | by CalInterval. This field should only be changed
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* | while the calibrator is idle. ie before csr
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* | CalRun is set.
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*/
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uint32_t lp4rl; /*
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* LPDDR4 Dram Read Latency.
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* Applicable only if dramtype == LPDDR4.
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* This variable is used to calculate LPDDR4 mr2-OP[2:0]
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* set in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
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* definition of MR.
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* Determine values based on your DRAM part's supported
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* speed and latency bin.
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* Default: calculated based on user_input_basic.frequency
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* and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write
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* Latencies".
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* Lowest latency selected when more than one latency can be
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* used. For example given configuration for LPDDR4, x16,
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* NoDbi and DDR533, RL=10 is selected rather than 14.
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*/
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uint32_t lp4wl; /*
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* LPDDR4 Dram Write Latency.
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* Applicable only if dramtype == LPDDR4.
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* This variable is used to calculate LPDDR4 mr2-OP[5:3]
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* set in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
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* definition of MR.
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* Determine values based on your DRAM part's supported
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* speed and latency bin.
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* Default: calculated based on user_input_basic.frequency
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* and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write
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* Latencies".
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* Lowest latency selected when more than one latency can be
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* used.
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*/
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uint32_t lp4wls; /*
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* LPDDR4 Dram WL Set.
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* Applicable only if dramtype == LPDDR4.
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* This variable is used to calculate LPDDR4 mr2-OP[6] set
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* in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
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* definition of MR.
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* Determine value based on Memory controllers requirement
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* of DRAM State after PHY training.
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*
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* Value | Description
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* --- | ---
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* 0x0 | WL Set "A" (default)
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*/
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uint32_t lp4dbird; /*
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* LPDDR4 Dram DBI-Read Enable.
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* Applicable only if dramtype == LPDDR4.
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* Determine if you require to using DBI for the given
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* PState.
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* If Read DBI is not used PHY receivers are turned off to
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* save power.
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* This variable is used to calculate LPDDR4 mr3-OP[6] set
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* in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* PHY register DMIPinPresent is programmed based on this
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* parameter.
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* Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
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* definition of MR.
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*
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* Value | Description
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* --- | ---
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* 0x0 | Disabled (default)
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* 0x1 | Enabled
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*/
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uint32_t lp4dbiwr; /*
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* LPDDR4 Dram DBI-Write Enable.
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* Applicable only if dramtype == LPDDR4.
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* This variable is used to calculate LPDDR4 mr3-OP[7] set
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* in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
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* definition of MR.
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*
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* Value | Description
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* --- | ---
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* 0x0 | Disabled (default)
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* 0x1 | Enabled
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*/
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uint32_t lp4nwr; /*
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* LPDDR4 Write-Recovery for Auto- Pre-charge commands.
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* Applicable only if dramtype == LPDDR4.
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* This variable is used to calculate LPDDR4 mr1-OP[6:4] set
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* in the messageBlock.
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* The training firmware will set DRAM MR according to MR
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* value in the messageBlock at the end of training.
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* Please refer to JEDEC JESD209-4A (LPDDR4) Spec for
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* definition of MR.
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* Determine values based on your DRAM part's supported
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* speed and latency bin.
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* Default: calculated based on user_input_basic.frequency
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* and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write
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* Latencies".
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* Lowest latency selected when more than one latency can be
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* used.
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*
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* Binary Value | Description
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* --- | ---
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* 000 | nWR = 6 (default)
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* 001 | nWR = 10
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* 010 | nWR = 16
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* 011 | nWR = 20
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* 100 | nWR = 24
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* 101 | nWR = 30
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* 110 | nWR = 34
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* 111 | nWR = 40
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*/
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uint32_t lp4lowpowerdrv; /*
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* Configure output Driver in Low power mode.
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* Feature only supported for Hard Macro Family E (HME).
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* Use NMOS Pull-up for Low-Power IO.
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* Not valid here
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*/
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uint32_t drambyteswap; /*
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* DRAM Oscillator count source mapping for skip_training.
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* The PHY supports swapping of DRAM oscillator count values
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* between paired DBytes for the purpose of tDQSDQ DRAM
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* Drift Compensation(DDC).
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* Each DByte has a register bit to control the source of
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* the oscillator count value used to perform tDQSDQ Drift
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* compensation.
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* On silicon the training firmware will determine the DByte
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* swap and program PptCtlStatic register to select
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* oscillator count source. When skip_train is used,
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* training firmware is skipped thus manual programming may
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* be required depending on configuration.
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* The default hardware configuration is for odd Dbyte
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* instance n to use oscillator count values from its paired
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* Dbyte instance n-1. So Dbyte1 will use the oscillator
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* count values from Dbyte0, Dbyte3 will use Dbyte2 and so
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* on. This is required for DRAM Data width =16.
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|
* Each bit of this field corresponds to a DBYTE:
|
|
* - bit-0 = setting for DBYTE0
|
|
* - bit-1 = setting for DBYTE1
|
|
* - bit-2 = setting for DBYTE2
|
|
* - . . .
|
|
* - bit-n = setting for DBYTEn
|
|
* By setting the associated bit for each DByte to 1, PHY
|
|
* will use non-default source for count value.
|
|
* - for even Dbytes, non-default source is to use the odd
|
|
* pair count value.
|
|
* - for odd Dbytes, no-default source to use data
|
|
* received directly from the DRAM.
|
|
* Byte swapping must be the same across different ranks.
|
|
* Default value: 0x0
|
|
* If Byte mode devices are indicated via the x8mode
|
|
* messageBlock parameter, this variable is ignored as PHY
|
|
* only supports a limited configuration set based on Byte
|
|
* mode configuration.
|
|
*
|
|
* Example:
|
|
* DramByteSwap = 0x03 - Dbyte0: use count values from
|
|
* Dbyte1, Dbyte1 uses count values received directly
|
|
* received from DRAM.
|
|
* Rest of Dbytes have default source for DRAM oscilator
|
|
* count.
|
|
*/
|
|
|
|
uint32_t rxenbackoff; /*
|
|
* Determines the Placement of PHY Read Gate signal.
|
|
* Only used in LPDDR4 when lp4rxpreamblemode==0 (static
|
|
* preamble) for skip_train==true.
|
|
* For other dramtypes or LPDDR4-toggling-preamble no
|
|
* options are available and PhyInit will set position as
|
|
* required. See source code in
|
|
* ddrphy_phyinit_c_initphyconfig() to see how the
|
|
* RxEnBackOff register is set.
|
|
* For skip_train==false, FW will set the position based on
|
|
* Preamble.
|
|
* We recommend keeping this setting at default value.
|
|
* SI analysis is required to determine if default value
|
|
* needs to be changed.
|
|
*
|
|
* Value | Description
|
|
* ----- | ---
|
|
* 0x1 | Position read gate 1UI from the first valid edge
|
|
* | of DQS_t (LPDDR4 Static preamble only) (default)
|
|
*/
|
|
|
|
uint32_t trainsequencectrl; /*
|
|
* Firmware Training Sequence Control.
|
|
* This input is used to program sequencectrl in
|
|
* messageBlock.
|
|
* It controls the training stages executed by firmware.
|
|
* For production silicon we recommend to use default value
|
|
* programmed by PhyInit.
|
|
*/
|
|
|
|
uint32_t snpsumctlopt; /*
|
|
* Enable Fast Frequency Change (FFC) Optimizations
|
|
* specific to UMCTL2 (DDRCTRL).
|
|
* Not valid for dimmtype=NODIMM.
|
|
* Consult DDRCTRL documentation in Reference Manual to
|
|
* ensure when optimizations can be enabled.
|
|
*
|
|
* Value | Description
|
|
* ----- | ---
|
|
* 0 | Disable FFC MRW optimization (default)
|
|
*/
|
|
|
|
uint32_t snpsumctlf0rc5x; /*
|
|
* F0RX5x RCD Control Word when using Fast Frequency
|
|
* Change(FFC) optimizations specific to UMCTL2
|
|
* Not valid for dimmtype=NODIMM.
|
|
* Only valid for when SnpsUmctlOpt=1.
|
|
* When UMCTL2 optimizations are enabled PHY will perform
|
|
* RCD MRW during fast frequency change request.
|
|
* The correct RCD control word value for each PState must
|
|
* be programmed in this field.
|
|
* Consult the RCD spec and UMCTL documentation to
|
|
* determine the correct value based on DRAM configuration
|
|
* and operating speed.
|
|
*/
|
|
|
|
uint32_t txslewrisedq; /*
|
|
* Pull-up slew rate control for DBYTE Tx.
|
|
* Value specified here will be written to register
|
|
* TxSlewRate.TxPreP by PhyInit.
|
|
* See register description for more information.
|
|
*/
|
|
|
|
uint32_t txslewfalldq; /*
|
|
* Pull-down slew rate control for DBYTE Tx.
|
|
* Value specified here will be written to
|
|
* TxSlewRate.TxPreN by PhyInit.
|
|
* See register description for more information.
|
|
*/
|
|
|
|
uint32_t txslewriseac; /*
|
|
* Pull-up slew rate control for ANIB Tx.
|
|
* Value specified here will be written to
|
|
* ATxSlewRate.ATxPreP.
|
|
* See register description for more information.
|
|
*/
|
|
|
|
uint32_t txslewfallac; /*
|
|
* Pull-down slew rate control for ANIB Tx.
|
|
* Value specified here will be written to
|
|
* ATxSlewRate.ATxPreN.
|
|
* See register description for more information.
|
|
*/
|
|
|
|
uint32_t disableretraining; /*
|
|
* Disable PHY DRAM Drift compensation re-training.
|
|
* Only applied to LPDDR4. No retraining is required in
|
|
* DDR4/3.
|
|
* Disable PHY re-training during DFI frequency change
|
|
* requests in LPDDR4.
|
|
* The purpose of retraining is to compensate for drift in
|
|
* the DRAM.
|
|
* Determine based on SI analysis and DRAM datasheet if
|
|
* retraining can be disabled.
|
|
*
|
|
* Value | Description
|
|
* ----- | ---
|
|
* 0x1 | Disable retraining
|
|
* 0x0 | Enable retraining
|
|
*/
|
|
|
|
uint32_t disablephyupdate; /*
|
|
* Disable DFI PHY Update feature.
|
|
* Only effects LPDDR4.
|
|
* Disable DFI PHY Update feature. When set PHY will not
|
|
* assert dfi0/1_phyupd_req.
|
|
*
|
|
* Value | Description
|
|
* ----- | ---
|
|
* 0x1 | Disable DFI PHY Update
|
|
* 0x0 | Enable DFI PHY Update
|
|
*/
|
|
|
|
uint32_t enablehighclkskewfix; /*
|
|
* Enable alternative PIE program.
|
|
* If enabled the PIE reinitializes the FIFO pointers a
|
|
* second time due for designs with large skew between
|
|
* chiplet DfiClk branches. If enabled PIE latencies in all
|
|
* protocols are increased by 60 DfiClks.
|
|
*
|
|
* Value | Description
|
|
* ----- | ---
|
|
* 0x0 | Disable (default)
|
|
*/
|
|
|
|
uint32_t disableunusedaddrlns; /*
|
|
* Turn off or tristate Address Lanes when possible.
|
|
*
|
|
* When enabled, PHY will tristate unused address lanes to
|
|
* save power when possible by using Acx4AnibDis and
|
|
* AForceTriCont registers.
|
|
* This feature is only implemented for the default PHY
|
|
* Address bump mapping and Ranks must be populated in
|
|
* order. ie Rank1 cannot be used if Rank0 is unpopulated.
|
|
* For alternative bump mapping follow the following
|
|
* guideline to achieve maximum power savings:
|
|
* - For each unused BP_A bump program AForceTriCont[4:0]
|
|
* bits based on register description.
|
|
* - if all lanes of an Anib are unused _AND_ ANIB is not
|
|
* the first or last instance set bit associated with
|
|
* the instance in Acs4AnibDis registers. see register
|
|
* description for details.
|
|
*
|
|
* Value | Description
|
|
* ----- | ---
|
|
* 0x1 | Enable
|
|
*/
|
|
|
|
uint32_t phyinitsequencenum; /*
|
|
* Switches between supported phyinit training sequences.
|
|
*
|
|
* Value | Description
|
|
* ----- | ---
|
|
* 0x0 | Minimizes number of Imem/Dmem loads (default)
|
|
*/
|
|
|
|
uint32_t enabledficspolarityfix;/*
|
|
* Enable alternative PIE program.
|
|
* Set to 1 if PUB_VERSION <2.43a, otherwise set to 0. If
|
|
* enabled the PIE programs Dfi{Rd,Wr}DataCsDestMap CSR's
|
|
* to default values 0x00E4 before running PPT.
|
|
* Before exiting PPT, PIE will restore
|
|
* Dfi{Rd,Wr}DataCsDestMap CSR's to 0x00E1.
|
|
*
|
|
* Value | Description
|
|
* ----- | ---
|
|
* 0x0 | Disable (default)
|
|
*/
|
|
|
|
uint32_t phyvref; /*
|
|
* Must be programmed with the Vref level to be used by the
|
|
* PHY during reads.
|
|
* The units of this field are a percentage of VDDQ
|
|
* according to the following equation:
|
|
* Receiver Vref = VDDQ*phyvref[6:0]/128
|
|
* For example to set Vref at 0.75*VDDQ, set this field to
|
|
* 0x60.
|
|
* For digital simulation, any legal value can be used. For
|
|
* silicon, the users must calculate the analytical Vref by
|
|
* using the impedances, terminations, and series resistance
|
|
* present in the system.
|
|
*/
|
|
|
|
uint32_t sequencectrl; /*
|
|
* Controls the training steps to be run. Each bit
|
|
* corresponds to a training step.
|
|
* If the bit is set to 1, the training step will run.
|
|
* If the bit is set to 0, the training step will be
|
|
* skipped.
|
|
* Training step to bit mapping:
|
|
* sequencectrl[0] = Run DevInit - Device/phy
|
|
* initialization. Should always be set.
|
|
* sequencectrl[1] = Run WrLvl - Write leveling
|
|
* sequencectrl[2] = Run RxEn - Read gate training
|
|
* sequencectrl[3] = Run RdDQS1D - 1d read dqs training
|
|
* sequencectrl[4] = Run WrDQ1D - 1d write dq training
|
|
* sequencectrl[5] = RFU, must be zero
|
|
* sequencectrl[6] = RFU, must be zero
|
|
* sequencectrl[7] = RFU, must be zero
|
|
* sequencectrl[8] = Run RdDeskew - Per lane read dq deskew
|
|
* training
|
|
* sequencectrl[9] = Run MxRdLat - Max read latency training
|
|
* sequencectrl[10] = RFU, must be zero
|
|
* sequencectrl[11] = RFU, must be zero
|
|
* sequencectrl[12] = RFU, must be zero
|
|
* sequencectrl[13] = RFU, must be zero
|
|
* sequencectrl[15-14] = RFU, must be zero
|
|
*/
|
|
};
|
|
|
|
/*
|
|
* Structure for mode register user inputs
|
|
*
|
|
* The following data structure must be set and completed correctly so that the PhyInit software
|
|
* package can accurate fill message block structure.
|
|
* Only some mrx are used per DDR type, on related width:
|
|
* - DDR3: mr0..2 are used (16-bits values)
|
|
* - DDR4: mr0..6 are used (16-bits values)
|
|
* - LPDDR4: mr1..4 and mr11..22 are used (8-bits values)
|
|
*/
|
|
struct user_input_mode_register {
|
|
uint32_t mr0;
|
|
uint32_t mr1;
|
|
uint32_t mr2;
|
|
uint32_t mr3;
|
|
uint32_t mr4;
|
|
uint32_t mr5;
|
|
uint32_t mr6;
|
|
uint32_t mr11;
|
|
uint32_t mr12;
|
|
uint32_t mr13;
|
|
uint32_t mr14;
|
|
uint32_t mr22;
|
|
};
|
|
|
|
/*
|
|
* Structure for swizzle user inputs
|
|
*
|
|
* The following data structure must be set and completed correctly sothat the PhyInit software
|
|
* package can accurate set swizzle (IO muxing) config.
|
|
* Only some swizzles are used per DDR type:
|
|
* - DDR3/DDR4: swizzle 0..32 are used
|
|
* - 26 for hwtswizzle
|
|
* - 7 for acswizzle
|
|
* - LPDDR4: swizzle 0..43 are used
|
|
* - 8 per byte for dqlnsel (total 32)
|
|
* - 6 for mapcaatodfi
|
|
* - 6 for mapcabtodfi
|
|
*/
|
|
#define NB_HWT_SWIZZLE 26U
|
|
#define NB_AC_SWIZZLE 7U
|
|
#define NB_DQLNSEL_SWIZZLE_PER_BYTE 8U
|
|
#define NB_MAPCAATODFI_SWIZZLE 6U
|
|
#define NB_MAPCABTODFI_SWIZZLE 6U
|
|
#define NB_SWIZZLE 44
|
|
struct user_input_swizzle {
|
|
uint32_t swizzle[NB_SWIZZLE];
|
|
};
|
|
|
|
#endif /* DDRPHY_PHYINIT_STRUCT_H */
|