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Currently links between documents are using the format: <path/to/><filename>.rst This was required for services like GitHub because they render each document in isolation - linking to another document is like linking to any other file, just provide the full path. However, with the new approach, the .rst files are only the raw source for the documents. Once the documents have been rendered the output is now in another format (HTML in our case) and so, when linking to another document, the link must point to the rendered version and not the .rst file. The RST spec provides a few methods for linking between content. The parent of this patch enabled the automatic creation of anchors for document titles - we will use these anchors as the targets for our links. Additional anchors can be added by hand if needed, on section and sub-section titles, for example. An example of this new format, for a document with the title "Firmware Design" is :ref:`Firmware Design`. One big advantage of this is that anchors are not dependent on paths. We can then move documents around, even between directories, without breaking any links between documents. Links will need to be updated only if the title of a document changes. Change-Id: I9e2340a61dd424cbd8fd1ecc2dc166f460d81703 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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3.6 KiB
ReStructuredText
94 lines
3.6 KiB
ReStructuredText
Arm SiP Services
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================
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This document enumerates and describes the Arm SiP (Silicon Provider) services.
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SiP services are non-standard, platform-specific services offered by the silicon
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implementer or platform provider. They are accessed via ``SMC`` ("SMC calls")
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instruction executed from Exception Levels below EL3. SMC calls for SiP
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services:
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- Follow `SMC Calling Convention`_;
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- Use SMC function IDs that fall in the SiP range, which are ``0xc2000000`` -
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``0xc200ffff`` for 64-bit calls, and ``0x82000000`` - ``0x8200ffff`` for 32-bit
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calls.
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The Arm SiP implementation offers the following services:
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- Performance Measurement Framework (PMF)
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- Execution State Switching service
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Source definitions for Arm SiP service are located in the ``arm_sip_svc.h`` header
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file.
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Performance Measurement Framework (PMF)
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---------------------------------------
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The :ref:`Performance Measurement Framework <firmware_design_pmf>`
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allows callers to retrieve timestamps captured at various paths in TF-A
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execution.
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Execution State Switching service
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---------------------------------
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Execution State Switching service provides a mechanism for a non-secure lower
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Exception Level (either EL2, or NS EL1 if EL2 isn't implemented) to request to
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switch its execution state (a.k.a. Register Width), either from AArch64 to
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AArch32, or from AArch32 to AArch64, for the calling CPU. This service is only
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available when Trusted Firmware-A (TF-A) is built for AArch64 (i.e. when build
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option ``ARCH`` is set to ``aarch64``).
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``ARM_SIP_SVC_EXE_STATE_SWITCH``
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Arguments:
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uint32_t Function ID
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uint32_t PC hi
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uint32_t PC lo
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uint32_t Cookie hi
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uint32_t Cookie lo
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Return:
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uint32_t
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The function ID parameter must be ``0x82000020``. It uniquely identifies the
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Execution State Switching service being requested.
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The parameters *PC hi* and *PC lo* defines upper and lower words, respectively,
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of the entry point (physical address) at which execution should start, after
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Execution State has been switched. When calling from AArch64, *PC hi* must be 0.
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When execution starts at the supplied entry point after Execution State has been
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switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
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0 and 1, respectively. When calling from AArch64, *Cookie hi* must be 0.
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This call can only be made on the primary CPU, before any secondaries were
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brought up with ``CPU_ON`` PSCI call. Otherwise, the call will always fail.
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The effect of switching execution state is as if the Exception Level were
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entered for the first time, following power on. This means CPU registers that
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have a defined reset value by the Architecture will assume that value. Other
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registers should not be expected to hold their values before the call was made.
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CPU endianness, however, is preserved from the previous execution state. Note
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that this switches the execution state of the calling CPU only. This is not a
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substitute for PSCI ``SYSTEM_RESET``.
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The service may return the following error codes:
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- ``STATE_SW_E_PARAM``: If any of the parameters were deemed invalid for
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a specific request.
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- ``STATE_SW_E_DENIED``: If the call is not successful, or when TF-A is
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built for AArch32.
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If the call is successful, the caller wouldn't observe the SMC returning.
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Instead, execution starts at the supplied entry point, with the CPU registers 0
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and 1 populated with the supplied *Cookie hi* and *Cookie lo* values,
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respectively.
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--------------
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*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.*
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.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
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