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4754925057
This patch is used to implement VAB to support for Agilex5 SoC FPGA. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I421f11225cd549f35f06e87b8ad2c44b716b2a78
54 lines
1.8 KiB
C
54 lines
1.8 KiB
C
/*
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* Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_VAB_H
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#define SOCFPGA_VAB_H
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#include <stdlib.h>
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#include "socfpga_fcs.h"
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struct fcs_hps_vab_certificate_data {
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uint32_t vab_cert_magic_num; /* offset 0x10 */
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uint32_t flags;
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uint8_t rsvd0_1[8];
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uint8_t fcs_sha384[FCS_SHA384_WORD_SIZE]; /* offset 0x20 */
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};
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struct fcs_hps_vab_certificate_header {
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uint32_t cert_magic_num; /* offset 0 */
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uint32_t cert_data_sz;
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uint32_t cert_ver;
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uint32_t cert_type;
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struct fcs_hps_vab_certificate_data d; /* offset 0x10 */
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/* keychain starts at offset 0x50 */
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};
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/* Macros */
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#define IS_BYTE_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
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#define BYTE_ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
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#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
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#define VAB_CERT_HEADER_SIZE sizeof(struct fcs_hps_vab_certificate_header)
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#define VAB_CERT_MAGIC_OFFSET offsetof(struct fcs_hps_vab_certificate_header, d)
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#define VAB_CERT_FIT_SHA384_OFFSET offsetof(struct fcs_hps_vab_certificate_data, fcs_sha384[0])
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#define SDM_CERT_MAGIC_NUM 0x25D04E7F
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#define CHUNKSZ_PER_WD_RESET (256 * 1024)
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/* SHA related return Macro */
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#define ENOVABIMG 1 /* VAB certificate not available */
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#define EIMGERR 2 /* Image format/size not valid */
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#define ETIMEOUT 3 /* Execution timeout */
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#define EPROCESS 4 /* Process error */
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#define EKEYREJECTED 5/* Key was rejected by service */
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/* Function Definitions */
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static size_t get_img_size(uint8_t *img_buf, size_t img_buf_sz);
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int socfpga_vendor_authentication(void **p_image, size_t *p_size);
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static uint32_t get_unaligned_le32(const void *p);
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void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
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unsigned char *output, unsigned int chunk_sz);
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#endif
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