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7618403110
This patch is used to implement system manager data support for Agilex5 SoC FPGA. 1. Initial SM bring up 2. Support Candence SDMMC/NAND/COMBO PHY 3. Updated product name -> Agilex5 4. Updated register address based on y22ww52.2 RTL Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I12712bddfb67e36a2bf56d2d98ea4ca3037f0a82
36 lines
875 B
C
36 lines
875 B
C
/*
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_SYSTEMMANAGER_H
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#define SOCFPGA_SYSTEMMANAGER_H
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#include "socfpga_plat_def.h"
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/* System Manager Register Map */
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#define SOCFPGA_SYSMGR_SDMMC 0x28
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/* Field Masking */
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#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
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#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
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#define IDLE_DATA_LWSOC2FPGA BIT(4)
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#define IDLE_DATA_SOC2FPGA BIT(0)
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#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
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#define SYSMGR_QSPI_REFCLK_MASK GENMASK(27, 0)
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#define SYSMGR_ECC_OCRAM_MASK BIT(1)
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#define SYSMGR_ECC_DDR0_MASK BIT(16)
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#define SYSMGR_ECC_DDR1_MASK BIT(17)
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/* Macros */
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#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
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+ (SOCFPGA_SYSMGR_##_reg))
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#endif /* SOCFPGA_SYSTEMMANAGER_H */
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