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https://github.com/ARM-software/arm-trusted-firmware.git
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9b8d813cc9
This patch is used to enable reset manager support for Agilex5 SoC FPGA. 1. Added HPS bridges support a. SOC2FPGA b. LWSOC2FPGA c. F2SDRAM d. F2SOC 2. Added EMULATOR support 3. Added WDT support 4. Updated product name -> Agilex5 5. Added SMP support Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Icab15b25f787fdccce1de75d102604db23beaf11
48 lines
1.7 KiB
C
48 lines
1.7 KiB
C
/*
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_F2SDRAMMANAGER_H
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#define SOCFPGA_F2SDRAMMANAGER_H
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#include "socfpga_plat_def.h"
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/* FPGA2SDRAM Register Map */
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#define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGINSTATUS0 0x14
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#define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTCLR0 0x54
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#define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTSET0 0x50
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#define FLAGOUTCLR0_F2SDRAM0_ENABLE (BIT(8))
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#define FLAGOUTSETCLR_F2SDRAM0_ENABLE (BIT(1))
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#define FLAGOUTSETCLR_F2SDRAM1_ENABLE (BIT(4))
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#define FLAGOUTSETCLR_F2SDRAM2_ENABLE (BIT(7))
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#define FLAGOUTSETCLR_F2SDRAM0_IDLEREQ (BIT(0))
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#define FLAGOUTSETCLR_F2SDRAM1_IDLEREQ (BIT(3))
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#define FLAGOUTSETCLR_F2SDRAM2_IDLEREQ (BIT(6))
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#define FLAGINSTATUS_F2SDRAM0_IDLEACK (BIT(1))
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#define FLAGINSTATUS_F2SDRAM1_IDLEACK (BIT(5))
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#define FLAGINSTATUS_F2SDRAM2_IDLEACK (BIT(9))
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#define FLAGINSTATUS_F2SDRAM0_CMDIDLE (BIT(2))
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#define FLAGINSTATUS_F2SDRAM1_CMDIDLE (BIT(6))
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#define FLAGINSTATUS_F2SDRAM2_CMDIDLE (BIT(10))
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#define FLAGINSTATUS_F2SDRAM0_NOCIDLE (BIT(0))
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#define FLAGINSTATUS_F2SDRAM1_NOCIDLE (BIT(4))
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#define FLAGINSTATUS_F2SDRAM2_NOCIDLE (BIT(8))
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#define FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN (BIT(2))
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#define FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN (BIT(5))
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#define FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN (BIT(8))
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#define FLAGINSTATUS_F2SOC_RESPEMPTY (BIT(3))
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#define FLAGINSTATUS_F2SDRAM0_RESPEMPTY (BIT(3))
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#define FLAGINSTATUS_F2SDRAM1_RESPEMPTY (BIT(7))
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#define FLAGINSTATUS_F2SDRAM2_RESPEMPTY (BIT(11))
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#define FLAGINSTATUS_F2S_FM_TRACKERIDLE (BIT(4))
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#define SOCFPGA_F2SDRAMMGR(_reg) (SOCFPGA_F2SDRAMMGR_REG_BASE \
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+ (SOCFPGA_F2SDRAMMGR_##_reg))
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#endif /* SOCFPGA_F2SDRAMMGR_H */
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