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https://github.com/ARM-software/arm-trusted-firmware.git
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ddaf02d171
This patch is used to implement sdmmc/nand/combo-phy driver to support Cadence IP for Agilex5 SoC FPGA. 1. Added SDMMC/NAND/COMBO-PHY support. 2. Updated product name -> Agilex5 3. Updated QSPI base address Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
42 lines
1.1 KiB
C
42 lines
1.1 KiB
C
/*
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* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SDMMC_H
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#define SDMMC_H
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#include <lib/mmio.h>
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#include "socfpga_handoff.h"
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#define PERIPHERAL_SDMMC_MASK 0x60
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#define PERIPHERAL_SDMMC_OFFSET 6
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#define DEFAULT_SDMMC_MAX_RETRIES 5
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#define SEND_SDMMC_OP_COND_MAX_RETRIES 100
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#define SDMMC_MULT_BY_512K_SHIFT 19
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static const unsigned char tran_speed_base[16] = {
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0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80
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};
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static const unsigned char sd_tran_speed_base[16] = {
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0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80
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};
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/* FUNCTION DEFINATION */
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/*
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* @brief SDMMC controller initialization function
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*
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* @hoff_ptr: Pointer to the hand-off data
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* Return: 0 on success, a negative errno on failure
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*/
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int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params,
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struct mmc_device_info *info);
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int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
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unsigned int width, unsigned int flags,
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struct mmc_device_info *device_info);
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void sdmmc_pin_config(void);
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#endif
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