arm-trusted-firmware/plat/intel/soc/common/drivers/nand/nand.h
Jit Loon Lim ddaf02d171 feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
	1. Added SDMMC/NAND/COMBO-PHY support.
	2. Updated product name -> Agilex5
	3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
2023-07-05 10:11:11 +08:00

22 lines
425 B
C

/*
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DDR_H
#define DDR_H
#include <lib/mmio.h>
#include "socfpga_handoff.h"
/* FUNCTION DEFINATION */
/*
* @brief Nand controller initialization function
*
* @hoff_ptr: Pointer to the hand-off data
* Return: 0 on success, a negative errno on failure
*/
int nand_init(handoff *hoff_ptr);
#endif