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https://github.com/ARM-software/arm-trusted-firmware.git
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7931d3322d
This patch is used to enable platform enablement for Agilex5 SoC FPGA. New feature: 1. Added ATF->Zephyr boot option 2. Added xlat_v2 for MMU 3. Added ATF->Linux boot option 4. Added SMP support 5. Added HPS bridges support 6. Added EMULATOR support 7. Added DDR support 8. Added GICv3 Redistirbution init 9. Added SDMMC/NAND/Combo Phy support 10. Updated GIC as secure access 11. Added CCU driver support 12. Updated product name -> Agilex5 13. Updated register address based on y22ww52.2 RTL 14. Updated system counter freq to 400MHz Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009
215 lines
5.2 KiB
ArmAsm
215 lines
5.2 KiB
ArmAsm
/*
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* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <platform_def.h>
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#include <el3_common_macros.S>
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.globl plat_secondary_cold_boot_setup
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.globl platform_is_primary_cpu
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl plat_secondary_cpus_bl31_entry
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.globl plat_get_my_entrypoint
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* Wait until the it gets reset signal from rstmgr gets populated */
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poll_mailbox:
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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mov_imm x0, PLAT_SEC_ENTRY
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cbz x0, poll_mailbox
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br x0
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#else
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wfi
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mov_imm x0, PLAT_SEC_ENTRY
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ldr x1, [x0]
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mov_imm x2, PLAT_CPUID_RELEASE
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ldr x3, [x2]
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mrs x4, mpidr_el1
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and x4, x4, #0xff
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cmp x3, x4
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b.ne poll_mailbox
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br x1
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#endif
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endfunc plat_secondary_cold_boot_setup
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#if ((PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10) || \
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(PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || \
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(PLATFORM_MODEL == PLAT_SOCFPGA_N5X))
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func platform_is_primary_cpu
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc platform_is_primary_cpu
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#else
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func platform_is_primary_cpu
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #(PLAT_PRIMARY_CPU_A76)
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b.eq primary_cpu
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cmp x0, #(PLAT_PRIMARY_CPU_A55)
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b.eq primary_cpu
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primary_cpu:
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cset x0, eq
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ret
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endfunc platform_is_primary_cpu
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#endif
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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b platform_is_primary_cpu
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endfunc plat_is_my_cpu_primary
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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add x0, x1, x0, LSR #8
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#else
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add x0, x1, x0, LSR #6
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#endif
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ret
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endfunc plat_my_core_pos
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func warm_reset_req
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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bl plat_is_my_cpu_primary
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cbnz x0, warm_reset
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warm_reset:
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mov_imm x1, PLAT_SEC_ENTRY
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str xzr, [x1]
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mrs x1, rmr_el3
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orr x1, x1, #0x02
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msr rmr_el3, x1
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isb
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dsb sy
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#else
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str xzr, [x4]
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bl plat_is_my_cpu_primary
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cbz x0, cpu_in_wfi
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mov_imm x1, PLAT_SEC_ENTRY
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str xzr, [x1]
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mrs x1, rmr_el3
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orr x1, x1, #0x02
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msr rmr_el3, x1
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isb
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dsb sy
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cpu_in_wfi:
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wfi
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b cpu_in_wfi
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#endif
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endfunc warm_reset_req
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/* TODO: Zephyr warm reset test */
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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func plat_get_my_entrypoint
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ldr x4, =L2_RESET_DONE_REG
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ldr x5, [x4]
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ldr x1, =PLAT_L2_RESET_REQ
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cmp x1, x5
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b.eq zephyr_reset_req
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mov_imm x1, PLAT_SEC_ENTRY
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ldr x0, [x1]
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ret
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zephyr_reset_req:
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ldr x0, =0x00
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ret
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endfunc plat_get_my_entrypoint
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#else
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func plat_get_my_entrypoint
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ldr x4, =L2_RESET_DONE_REG
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ldr x5, [x4]
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ldr x1, =L2_RESET_DONE_STATUS
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cmp x1, x5
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b.eq warm_reset_req
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mov_imm x1, PLAT_SEC_ENTRY
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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#endif
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, CRASH_CONSOLE_BASE
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mov_imm x1, PLAT_UART_CLOCK
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mov_imm x2, PLAT_BAUDRATE
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b console_16550_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, CRASH_CONSOLE_BASE
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b console_16550_core_putc
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov_imm x0, CRASH_CONSOLE_BASE
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b console_16550_core_flush
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endfunc plat_crash_console_flush
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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/* --------------------------------------------------------
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* macro plat_secondary_cpus_bl31_entry;
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*
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* el3_entrypoint_common init param configuration.
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* Called very early in the secondary cores boot process.
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* --------------------------------------------------------
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*/
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func plat_secondary_cpus_bl31_entry
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el3_entrypoint_common \
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_init_sctlr=0 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=runtime_exceptions \
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_pie_fixup_size=BL31_LIMIT - BL31_BASE
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endfunc plat_secondary_cpus_bl31_entry
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