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https://github.com/ARM-software/arm-trusted-firmware.git
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7931d3322d
This patch is used to enable platform enablement for Agilex5 SoC FPGA. New feature: 1. Added ATF->Zephyr boot option 2. Added xlat_v2 for MMU 3. Added ATF->Linux boot option 4. Added SMP support 5. Added HPS bridges support 6. Added EMULATOR support 7. Added DDR support 8. Added GICv3 Redistirbution init 9. Added SDMMC/NAND/Combo Phy support 10. Updated GIC as secure access 11. Added CCU driver support 12. Updated product name -> Agilex5 13. Updated register address based on y22ww52.2 RTL 14. Updated system counter freq to 400MHz Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009
107 lines
3.8 KiB
Makefile
107 lines
3.8 KiB
Makefile
#
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# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_INCLUDES := \
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-Iplat/intel/soc/agilex5/include/ \
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-Iplat/intel/soc/common/drivers/ \
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-Iplat/intel/soc/common/include/
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# GIC-600 configuration
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GICV3_SUPPORT_GIC600 := 1
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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AGX5_GICv3_SOURCES := \
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${GICV3_SOURCES} \
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plat/common/plat_gicv3.c
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PLAT_BL_COMMON_SOURCES := \
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${AGX5_GICv3_SOURCES} \
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drivers/cadence/combo_phy/cdns_combo_phy.c \
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drivers/cadence/emmc/cdns_sdmmc.c \
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drivers/cadence/nand/cdns_nand.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/ti/uart/aarch64/16550_console.S \
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plat/intel/soc/common/aarch64/platform_common.c \
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plat/intel/soc/common/aarch64/plat_helpers.S \
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plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
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plat/intel/soc/common/drivers/combophy/combophy.c \
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plat/intel/soc/common/drivers/sdmmc/sdmmc.c \
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plat/intel/soc/common/drivers/ddr/ddr.c \
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plat/intel/soc/common/drivers/nand/nand.c \
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plat/intel/soc/common/socfpga_delay_timer.c
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BL2_SOURCES += \
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common/desc_image_load.c \
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lib/xlat_tables_v2/aarch64/enable_mmu.S \
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lib/xlat_tables_v2/xlat_tables_context.c \
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lib/xlat_tables_v2/xlat_tables_core.c \
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lib/xlat_tables_v2/aarch64/xlat_tables_arch.c \
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lib/xlat_tables_v2/xlat_tables_utils.c \
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drivers/mmc/mmc.c \
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drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
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drivers/io/io_storage.c \
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drivers/io/io_block.c \
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drivers/io/io_fip.c \
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drivers/io/io_mtd.c \
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drivers/partition/partition.c \
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drivers/partition/gpt.c \
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drivers/synopsys/emmc/dw_mmc.c \
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lib/cpus/aarch64/cortex_a55.S \
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lib/cpus/aarch64/cortex_a76.S \
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plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
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plat/intel/soc/agilex5/soc/agilex5_memory_controller.c \
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plat/intel/soc/agilex5/soc/agilex5_mmc.c \
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plat/intel/soc/agilex5/soc/agilex5_pinmux.c \
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plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
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plat/intel/soc/common/bl2_plat_mem_params_desc.c \
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plat/intel/soc/common/socfpga_image_load.c \
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plat/intel/soc/common/socfpga_storage.c \
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plat/intel/soc/common/socfpga_vab.c \
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plat/intel/soc/common/soc/socfpga_emac.c \
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plat/intel/soc/common/soc/socfpga_firewall.c \
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plat/intel/soc/common/soc/socfpga_handoff.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c \
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plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
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plat/intel/soc/agilex5/bl2_plat_setup.c \
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plat/intel/soc/common/drivers/wdt/watchdog.c
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include lib/zlib/zlib.mk
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PLAT_INCLUDES += -Ilib/zlib
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BL2_SOURCES += $(ZLIB_SOURCES)
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BL31_SOURCES += \
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drivers/arm/cci/cci.c \
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${XLAT_TABLES_LIB_SRCS} \
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lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a55.S \
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lib/cpus/aarch64/cortex_a76.S \
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plat/common/plat_psci_common.c \
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plat/intel/soc/agilex5/bl31_plat_setup.c \
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plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
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plat/intel/soc/common/socfpga_psci.c \
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plat/intel/soc/common/socfpga_sip_svc.c \
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plat/intel/soc/common/socfpga_sip_svc_v2.c \
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plat/intel/soc/common/socfpga_topology.c \
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plat/intel/soc/common/sip/socfpga_sip_ecc.c \
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plat/intel/soc/common/sip/socfpga_sip_fcs.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c
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# Configs for A76 and A55
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HW_ASSISTED_COHERENCY := 1
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USE_COHERENT_MEM := 0
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CTX_INCLUDE_AARCH32_REGS := 0
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ERRATA_A55_1530923 := 1
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$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
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PROGRAMMABLE_RESET_ADDRESS := 0
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RESET_TO_BL2 := 1
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BL2_INV_DCACHE := 0
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MULTI_CONSOLE_API := 1
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