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a8bf898f02
This patch is used to implement power manager data support for Agilex5 SoC FPGA. 1. Added power manager support. 2. Updated product name -> Agilex5 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: If0630c5088a1bc63dff64b1aab225fc70effa6e3
83 lines
2.7 KiB
C
83 lines
2.7 KiB
C
/*
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* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef POWERMANAGER_H
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#define POWERMANAGER_H
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#include "socfpga_handoff.h"
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#define AGX5_PWRMGR_BASE 0x10d14000
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/* DSU */
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#define AGX5_PWRMGR_DSU_FWENCTL 0x0
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#define AGX5_PWRMGR_DSU_PGENCTL 0x4
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#define AGX5_PWRMGR_DSU_PGSTAT 0x8
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#define AGX5_PWRMGR_DSU_PWRCTLR 0xc
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#define AGX5_PWRMGR_DSU_PWRSTAT0 0x10
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#define AGX5_PWRMGR_DSU_PWRSTAT1 0x14
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/* DSU Macros*/
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#define AGX5_PWRMGR_DSU_FWEN(x) ((x) & 0xf)
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#define AGX5_PWRMGR_DSU_PGEN(x) ((x) & 0xf)
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#define AGX5_PWRMGR_DSU_PGEN_OUT(x) ((x) & 0xf)
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#define AGX5_PWRMGR_DSU_SINGLE_PACCEPT(x) ((x) & 0x1)
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#define AGX5_PWRMGR_DSU_SINGLE_PDENY(x) (((x) & 0x1) << 1)
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#define AGX5_PWRMGR_DSU_SINGLE_FSM_STATE(x) (((x) & 0xff) << 8)
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#define AGX5_PWRMGR_DSU_SINGLE_PCH_DONE(x) (((x) & 0x1) << 31)
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#define AGX5_PWRMGR_DSU_MULTI_PACTIVE_IN(x) ((x) & 0xff)
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#define AGX5_PWRMGR_DSU_MULTI_PACCEPT(x) (((x) & 0xff) << 8)
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#define AGX5_PWRMGR_DSU_MULTI_PDENY(x) (((x) & 0xff) << 16)
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#define AGX5_PWRMGR_DSU_MULTI_PCH_DONE(x) (((x) & 0x1) << 31)
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/* CPU */
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#define AGX5_PWRMGR_CPU_PWRCTLR0 0x18
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#define AGX5_PWRMGR_CPU_PWRCTLR1 0x20
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#define AGX5_PWRMGR_CPU_PWRCTLR2 0x28
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#define AGX5_PWRMGR_CPU_PWRCTLR3 0x30
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#define AGX5_PWRMGR_CPU_PWRSTAT0 0x1c
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#define AGX5_PWRMGR_CPU_PWRSTAT1 0x24
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#define AGX5_PWRMGR_CPU_PWRSTAT2 0x2c
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#define AGX5_PWRMGR_CPU_PWRSTAT3 0x34
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/* APS */
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#define AGX5_PWRMGR_APS_FWENCTL 0x38
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#define AGX5_PWRMGR_APS_PGENCTL 0x3C
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#define AGX5_PWRMGR_APS_PGSTAT 0x40
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/* PSS */
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#define AGX5_PWRMGR_PSS_FWENCTL 0x44
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#define AGX5_PWRMGR_PSS_PGENCTL 0x48
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#define AGX5_PWRMGR_PSS_PGSTAT 0x4c
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/* PSS Macros*/
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#define AGX5_PWRMGR_PSS_FWEN(x) ((x) & 0xff)
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#define AGX5_PWRMGR_PSS_PGEN(x) ((x) & 0xff)
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#define AGX5_PWRMGR_PSS_PGEN_OUT(x) ((x) & 0xff)
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/* MPU */
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#define AGX5_PWRMGR_MPU_PCHCTLR 0x50
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#define AGX5_PWRMGR_MPU_PCHSTAT 0x54
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#define AGX5_PWRMGR_MPU_BOOTCONFIG 0x58
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#define AGX5_PWRMGR_CPU_POWER_STATE_MASK 0x1E
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/* MPU Macros*/
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#define AGX5_PWRMGR_MPU_TRIGGER_PCH_DSU(x) ((x) & 0x1)
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#define AGX5_PWRMGR_MPU_TRIGGER_PCH_CPU(x) (((x) & 0xf) << 1)
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#define AGX5_PWRMGR_MPU_STATUS_PCH_CPU(x) (((x) & 0xf) << 1)
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/* Shared Macros */
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#define AGX5_PWRMGR(_reg) (AGX5_PWRMGR_BASE + \
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(AGX5_PWRMGR_##_reg))
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/* POWER MANAGER ERROR CODE */
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#define AGX5_PWRMGR_HANDOFF_PERIPHERAL -1
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#define AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY 0x0
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#define AGX5_PWRMGR_PSS_STAT_BUSY(x) (((x) & 0x000000FF) >> 0)
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int pss_sram_power_off(handoff *hoff_ptr);
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int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff);
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#endif
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