mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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1b1a3eb1ed
This patch is used to enable clock manager support for Agilex5 SoC FPGA. 1. Added clock manager support. 2. Updated product name -> Agilex5 3. Updated register address based on y22ww52.2 RTL 4. Standardized handoff handler. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b
150 lines
4.7 KiB
C
150 lines
4.7 KiB
C
/*
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CLOCKMANAGER_H
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#define CLOCKMANAGER_H
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#include "socfpga_handoff.h"
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/* Clock Manager Registers */
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#define CLKMGR_OFFSET 0x10d10000
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#define CLKMGR_CTRL 0x0
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#define CLKMGR_STAT 0x4
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#define CLKMGR_TESTIOCTROL 0x8
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#define CLKMGR_INTRGEN 0xc
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#define CLKMGR_INTRMSK 0x10
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#define CLKMGR_INTRCLR 0x14
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#define CLKMGR_INTRSTS 0x18
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#define CLKMGR_INTRSTK 0x1c
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#define CLKMGR_INTRRAW 0x20
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/* Main PLL Group */
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#define CLKMGR_MAINPLL 0x10d10024
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#define CLKMGR_MAINPLL_EN 0x0
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#define CLKMGR_MAINPLL_ENS 0x4
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#define CLKMGR_MAINPLL_BYPASS 0xc
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#define CLKMGR_MAINPLL_BYPASSS 0x10
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#define CLKMGR_MAINPLL_BYPASSR 0x14
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#define CLKMGR_MAINPLL_NOCCLK 0x1c
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#define CLKMGR_MAINPLL_NOCDIV 0x20
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#define CLKMGR_MAINPLL_PLLGLOB 0x24
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#define CLKMGR_MAINPLL_FDBCK 0x28
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#define CLKMGR_MAINPLL_MEM 0x2c
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#define CLKMGR_MAINPLL_MEMSTAT 0x30
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#define CLKMGR_MAINPLL_VCOCALIB 0x34
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#define CLKMGR_MAINPLL_PLLC0 0x38
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#define CLKMGR_MAINPLL_PLLC1 0x3c
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#define CLKMGR_MAINPLL_PLLC2 0x40
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#define CLKMGR_MAINPLL_PLLC3 0x44
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#define CLKMGR_MAINPLL_PLLM 0x48
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#define CLKMGR_MAINPLL_FHOP 0x4c
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#define CLKMGR_MAINPLL_SSC 0x50
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#define CLKMGR_MAINPLL_LOSTLOCK 0x54
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/* Peripheral PLL Group */
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#define CLKMGR_PERPLL 0x10d1007c
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#define CLKMGR_PERPLL_EN 0x0
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#define CLKMGR_PERPLL_ENS 0x4
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#define CLKMGR_PERPLL_BYPASS 0xc
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#define CLKMGR_PERPLL_EMACCTL 0x18
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#define CLKMGR_PERPLL_GPIODIV 0x1c
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#define CLKMGR_PERPLL_PLLGLOB 0x20
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#define CLKMGR_PERPLL_FDBCK 0x24
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#define CLKMGR_PERPLL_MEM 0x28
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#define CLKMGR_PERPLL_MEMSTAT 0x2c
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#define CLKMGR_PERPLL_PLLC0 0x30
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#define CLKMGR_PERPLL_PLLC1 0x34
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#define CLKMGR_PERPLL_VCOCALIB 0x38
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#define CLKMGR_PERPLL_PLLC2 0x3c
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#define CLKMGR_PERPLL_PLLC3 0x40
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#define CLKMGR_PERPLL_PLLM 0x44
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#define CLKMGR_PERPLL_LOSTLOCK 0x50
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/* Altera Group */
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#define CLKMGR_ALTERA 0x10d100d0
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#define CLKMGR_ALTERA_JTAG 0x0
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#define CLKMGR_ALTERA_EMACACTR 0x4
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#define CLKMGR_ALTERA_EMACBCTR 0x8
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#define CLKMGR_ALTERA_EMACPTPCTR 0xc
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#define CLKMGR_ALTERA_GPIODBCTR 0x10
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#define CLKMGR_ALTERA_S2FUSER0CTR 0x18
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#define CLKMGR_ALTERA_S2FUSER1CTR 0x1c
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#define CLKMGR_ALTERA_PSIREFCTR 0x20
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#define CLKMGR_ALTERA_EXTCNTRST 0x24
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#define CLKMGR_ALTERA_USB31CTR 0x28
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#define CLKMGR_ALTERA_DSUCTR 0x2c
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#define CLKMGR_ALTERA_CORE01CTR 0x30
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#define CLKMGR_ALTERA_CORE23CTR 0x34
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#define CLKMGR_ALTERA_CORE2CTR 0x38
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#define CLKMGR_ALTERA_CORE3CTR 0x3c
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/* Membus */
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#define CLKMGR_MEM_REQ BIT(24)
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#define CLKMGR_MEM_WR BIT(25)
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#define CLKMGR_MEM_ERR BIT(26)
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#define CLKMGR_MEM_WDAT_OFFSET 16
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#define CLKMGR_MEM_ADDR 0x4027
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#define CLKMGR_MEM_WDAT 0x80
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/* Clock Manager Macros */
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#define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001
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#define CLKMGR_STAT_BUSY_E_BUSY 0x1
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#define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0)
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#define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8)
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#define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16)
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#define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004
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#define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008
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#define CLKMGR_INTOSC_HZ 460000000
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/* Main PLL Macros */
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#define CLKMGR_MAINPLL_EN_RESET 0x0000005e
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#define CLKMGR_MAINPLL_ENS_RESET 0x0000005e
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/* Peripheral PLL Macros */
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#define CLKMGR_PERPLL_EN_RESET 0x040007FF
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#define CLKMGR_PERPLL_ENS_RESET 0x040007FF
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#define CLKMGR_PERPLL_EN_SDMMCCLK BIT(5)
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#define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff)
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/* Altera Macros */
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#define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff
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/* Shared Macros */
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#define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16)
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#define CLKMGR_PSRC_MAIN 0
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#define CLKMGR_PSRC_PER 1
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#define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0
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#define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1
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#define CLKMGR_PLLGLOB_PSRC_F2S 0x2
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#define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff)
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#define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001
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#define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002
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#define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
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#define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8)
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#define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
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#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff)
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#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000)
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#define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000
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typedef struct {
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uint32_t clk_freq_of_eosc1;
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uint32_t clk_freq_of_f2h_free;
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uint32_t clk_freq_of_cb_intosc_ls;
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} CLOCK_SOURCE_CONFIG;
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void config_clkmgr_handoff(handoff *hoff_ptr);
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uint32_t get_wdt_clk(void);
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uint32_t get_uart_clk(void);
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uint32_t get_mmc_clk(void);
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#endif
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