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3a2710dcab
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
36 lines
827 B
C
36 lines
827 B
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ERRATA_REPORT_H
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#define ERRATA_REPORT_H
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#ifndef __ASSEMBLER__
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/spinlock.h>
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#include <lib/utils_def.h>
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#if DEBUG
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void print_errata_status(void);
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#else
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static inline void print_errata_status(void) {}
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#endif
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void errata_print_msg(unsigned int status, const char *cpu, const char *id);
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int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
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#endif /* __ASSEMBLER__ */
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/* Errata status */
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#define ERRATA_NOT_APPLIES 0
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#define ERRATA_APPLIES 1
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#define ERRATA_MISSING 2
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/* Macro to get CPU revision code for checking errata version compatibility. */
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#define CPU_REV(r, p) ((r << 4) | p)
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#endif /* ERRATA_REPORT_H */
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