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https://github.com/ARM-software/arm-trusted-firmware.git
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ad0cbbf513
the dfi phy master setting need to be save/restore to make sure it aligned with the initial config. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Change-Id: I4f572b9aff9cc47a6c28524ce0fe03cdc66b88a1
295 lines
8.2 KiB
C
295 lines
8.2 KiB
C
/*
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* Copyright 2018-2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <dram.h>
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static void lpddr4_mr_write(uint32_t mr_rank, uint32_t mr_addr, uint32_t mr_data)
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{
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/*
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* 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there
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* is no outstanding MR transaction. No
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* writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1.
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*/
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while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1)
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;
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/*
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* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr,
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* MRCTRL0.mr_rank and (for MRWs)
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* MRCTRL1.mr_data to define the MR transaction.
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*/
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mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4));
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mmio_write_32(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
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mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31));
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}
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void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp,
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unsigned int fsp_index)
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{
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uint32_t mr, emr, emr2, emr3;
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uint32_t mr11, mr12, mr22, mr14;
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uint32_t val;
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uint32_t derate_backup[3];
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uint32_t (*mr_data)[8];
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uint32_t phy_master;
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/* 1. program targetd UMCTL2_REGS_FREQ1/2/3,already done, skip it. */
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/* 2. MR13.FSP-WR=1, MRW to update MR registers */
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mr_data = info->mr_table;
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mr = mr_data[fsp_index][0];
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emr = mr_data[fsp_index][1];
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emr2 = mr_data[fsp_index][2];
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emr3 = mr_data[fsp_index][3];
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mr11 = mr_data[fsp_index][4];
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mr12 = mr_data[fsp_index][5];
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mr22 = mr_data[fsp_index][6];
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mr14 = mr_data[fsp_index][7];
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val = (init_fsp == 1) ? 0x2 << 6 : 0x1 << 6;
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emr3 = (emr3 & 0x003f) | val | 0x0d00;
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/* 12. set PWRCTL.selfref_en=0 */
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mmio_clrbits_32(DDRC_PWRCTL(0), 0xf);
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phy_master = mmio_read_32(DDRC_DFIPHYMSTR(0));
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/* It is more safe to config it here */
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mmio_clrbits_32(DDRC_DFIPHYMSTR(0), 0x1);
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lpddr4_mr_write(3, 13, emr3);
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lpddr4_mr_write(3, 1, mr);
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lpddr4_mr_write(3, 2, emr);
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lpddr4_mr_write(3, 3, emr2);
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lpddr4_mr_write(3, 11, mr11);
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lpddr4_mr_write(3, 12, mr12);
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lpddr4_mr_write(3, 14, mr14);
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lpddr4_mr_write(3, 22, mr22);
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do {
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val = mmio_read_32(DDRC_MRSTAT(0));
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} while (val & 0x1);
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/* 3. disable AXI ports */
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mmio_write_32(DDRC_PCTRL_0(0), 0x0);
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/* 4.Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. */
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do {
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val = mmio_read_32(DDRC_PSTAT(0));
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} while (val != 0);
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/* 6.disable SBRCTL.scrub_en, skip if never enable it */
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/* 7.poll SBRSTAT.scrub_busy Q2: should skip phy master if never enable it */
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/* Disable phy master */
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#ifdef DFILP_SPT
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/* 8. disable DFI LP */
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/* DFILPCFG0.dfi_lp_en_sr */
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val = mmio_read_32(DDRC_DFILPCFG0(0));
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if (val & 0x100) {
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mmio_write_32(DDRC_DFILPCFG0(0), 0x0);
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do {
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val = mmio_read_32(DDRC_DFISTAT(0)); // dfi_lp_ack
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val2 = mmio_read_32(DDRC_STAT(0)); // operating_mode
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} while (((val & 0x2) == 0x2) && ((val2 & 0x7) == 3));
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}
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#endif
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/* 9. wait until in normal or power down states */
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do {
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/* operating_mode */
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val = mmio_read_32(DDRC_STAT(0));
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} while (((val & 0x7) != 1) && ((val & 0x7) != 2));
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/* 10. Disable automatic derating: derate_enable */
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val = mmio_read_32(DDRC_DERATEEN(0));
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derate_backup[0] = val;
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mmio_clrbits_32(DDRC_DERATEEN(0), 0x1);
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val = mmio_read_32(DDRC_FREQ1_DERATEEN(0));
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derate_backup[1] = val;
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mmio_clrbits_32(DDRC_FREQ1_DERATEEN(0), 0x1);
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val = mmio_read_32(DDRC_FREQ2_DERATEEN(0));
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derate_backup[2] = val;
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mmio_clrbits_32(DDRC_FREQ2_DERATEEN(0), 0x1);
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/* 11. disable automatic ZQ calibration */
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mmio_setbits_32(DDRC_ZQCTL0(0), BIT(31));
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mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31));
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mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31));
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/* 12. set PWRCTL.selfref_en=0 */
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mmio_clrbits_32(DDRC_PWRCTL(0), 0x1);
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/* 13.Poll STAT.operating_mode is in "Normal" (001) or "Power-down" (010) */
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do {
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val = mmio_read_32(DDRC_STAT(0));
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} while (((val & 0x7) != 1) && ((val & 0x7) != 2));
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/* 14-15. trigger SW SR */
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/* bit 5: selfref_sw, bit 6: stay_in_selfref */
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mmio_setbits_32(DDRC_PWRCTL(0), 0x60);
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/* 16. Poll STAT.selfref_state in "Self Refresh 1" */
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do {
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val = mmio_read_32(DDRC_STAT(0));
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} while ((val & 0x300) != 0x100);
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/* 17. disable dq */
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mmio_setbits_32(DDRC_DBG1(0), 0x1);
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/* 18. Poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty */
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do {
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val = mmio_read_32(DDRC_DBGCAM(0));
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val &= 0x30000000;
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} while (val != 0x30000000);
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/* 19. change MR13.FSP-OP to new FSP and MR13.VRCG to high current */
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emr3 = (((~init_fsp) & 0x1) << 7) | (0x1 << 3) | (emr3 & 0x0077) | 0x0d00;
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lpddr4_mr_write(3, 13, emr3);
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/* 20. enter SR Power Down */
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mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x20);
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/* 21. Poll STAT.selfref_state is in "SR Power down" */
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do {
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val = mmio_read_32(DDRC_STAT(0));
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} while ((val & 0x300) != 0x200);
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/* 22. set dfi_init_complete_en = 0 */
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/* 23. switch clock */
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/* set SWCTL.dw_done to 0 */
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mmio_write_32(DDRC_SWCTL(0), 0x0000);
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/* 24. program frequency mode=1(bit 29), target_frequency=target_freq (bit 29) */
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mmio_write_32(DDRC_MSTR2(0), fsp_index);
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/* 25. DBICTL for FSP-OP[1], skip it if never enable it */
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/* 26.trigger initialization in the PHY */
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/* Q3: if refresh level is updated, then should program */
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/* as updating refresh, need to toggle refresh_update_level signal */
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val = mmio_read_32(DDRC_RFSHCTL3(0));
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val = val ^ 0x2;
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mmio_write_32(DDRC_RFSHCTL3(0), val);
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/* Q4: only for legacy PHY, so here can skipped */
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/* dfi_frequency -> 0x1x */
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val = mmio_read_32(DDRC_DFIMISC(0));
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val &= 0xFE;
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val |= (fsp_index << 8);
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mmio_write_32(DDRC_DFIMISC(0), val);
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/* dfi_init_start */
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val |= 0x20;
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mmio_write_32(DDRC_DFIMISC(0), val);
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/* polling dfi_init_complete de-assert */
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do {
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val = mmio_read_32(DDRC_DFISTAT(0));
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} while ((val & 0x1) == 0x1);
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/* change the clock frequency */
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dram_clock_switch(info->timing_info->fsp_table[fsp_index], info->bypass_mode);
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/* dfi_init_start de-assert */
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mmio_clrbits_32(DDRC_DFIMISC(0), 0x20);
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/* polling dfi_init_complete re-assert */
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do {
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val = mmio_read_32(DDRC_DFISTAT(0));
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} while ((val & 0x1) == 0x0);
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/* 27. set ZQCTL0.dis_srx_zqcl = 1 */
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if (fsp_index == 0) {
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mmio_setbits_32(DDRC_ZQCTL0(0), BIT(30));
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} else if (fsp_index == 1) {
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mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30));
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} else {
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mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30));
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}
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/* 28,29. exit "self refresh power down" to stay "self refresh 2" */
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/* exit SR power down */
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mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x40);
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/* 30. Poll STAT.selfref_state in "Self refresh 2" */
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do {
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val = mmio_read_32(DDRC_STAT(0));
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} while ((val & 0x300) != 0x300);
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/* 31. change MR13.VRCG to normal */
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emr3 = (emr3 & 0x00f7) | 0x0d00;
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lpddr4_mr_write(3, 13, emr3);
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/* restore the PHY master */
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mmio_write_32(DDRC_DFIPHYMSTR(0), phy_master);
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/* 32. issue ZQ if required: zq_calib_short, bit 4 */
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/* polling zq_calib_short_busy */
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mmio_setbits_32(DDRC_DBGCMD(0), 0x10);
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do {
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val = mmio_read_32(DDRC_DBGSTAT(0));
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} while ((val & 0x10) != 0x0);
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/* 33. Reset ZQCTL0.dis_srx_zqcl=0 */
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if (fsp_index == 1)
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mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30));
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else if (fsp_index == 2)
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mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30));
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else
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mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(30));
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/* set SWCTL.dw_done to 1 and poll SWSTAT.sw_done_ack=1 */
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mmio_write_32(DDRC_SWCTL(0), 0x1);
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/* wait SWSTAT.sw_done_ack to 1 */
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do {
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val = mmio_read_32(DDRC_SWSTAT(0));
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} while ((val & 0x1) == 0x0);
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/* 34. set PWRCTL.stay_in_selfreh=0, exit SR */
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mmio_clrbits_32(DDRC_PWRCTL(0), 0x40);
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/* wait tXSR */
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/* 35. Poll STAT.selfref_state in "Idle" */
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do {
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val = mmio_read_32(DDRC_STAT(0));
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} while ((val & 0x300) != 0x0);
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#ifdef DFILP_SPT
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/* 36. restore dfi_lp.dfi_lp_en_sr */
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mmio_setbits_32(DDRC_DFILPCFG0(0), BIT(8));
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#endif
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/* 37. re-enable CAM: dis_dq */
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mmio_clrbits_32(DDRC_DBG1(0), 0x1);
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/* 38. re-enable automatic SR: selfref_en */
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mmio_setbits_32(DDRC_PWRCTL(0), 0x1);
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/* 39. re-enable automatic ZQ: dis_auto_zq=0 */
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/* disable automatic ZQ calibration */
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if (fsp_index == 1)
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mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31));
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else if (fsp_index == 2)
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mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31));
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else
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mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(31));
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/* 40. re-emable automatic derating: derate_enable */
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mmio_write_32(DDRC_DERATEEN(0), derate_backup[0]);
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mmio_write_32(DDRC_FREQ1_DERATEEN(0), derate_backup[1]);
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mmio_write_32(DDRC_FREQ2_DERATEEN(0), derate_backup[2]);
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/* 41. write 1 to PCTRL.port_en */
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mmio_write_32(DDRC_PCTRL_0(0), 0x1);
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/* 42. enable SBRCTL.scrub_en, skip if never enable it */
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}
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