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9c336f6118
Add the DDR frequency change support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: If1167785796b8678c351569b83d2922c66f6e530
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#define IMX_CCM_IP_BASE (IMX_CCM_BASE + 0xa000)
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#define DRAM_SEL_CFG (IMX_CCM_BASE + 0x9800)
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#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x00)
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#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x04)
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#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x08)
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#define PLL_FREQ_800M U(0x00ece580)
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#define PLL_FREQ_400M U(0x00ec6984)
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#define PLL_FREQ_167M U(0x00f5a406)
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void ddr_pll_bypass_100mts(void)
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{
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/* change the clock source of dram_alt_clk_root to source 2 --100MHz */
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16));
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x2 << 24));
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/* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x2 << 24) | (0x1 << 16));
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/* configure pll bypass mode */
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mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24));
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}
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void ddr_pll_bypass_400mts(void)
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{
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/* change the clock source of dram_alt_clk_root to source 1 --400MHz */
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16));
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x1 << 24) | (0x1 << 16));
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/* change the clock source of dram_apb_clk_root to source 3 --160MHz/2 */
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x3 << 24) | (0x1 << 16));
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/* configure pll bypass mode */
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mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24));
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}
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void ddr_pll_unbypass(void)
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{
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mmio_write_32(DRAM_SEL_CFG + 0x8, BIT(24));
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
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/* to source 4 --800MHz/5 */
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mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x4 << 16));
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}
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#if defined(PLAT_imx8mq)
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void dram_pll_init(unsigned int drate)
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{
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/* bypass the PLL */
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mmio_setbits_32(HW_DRAM_PLL_CFG0, 0x30);
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switch (drate) {
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case 3200:
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mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_800M);
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break;
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case 1600:
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mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_400M);
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break;
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case 667:
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mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_167M);
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break;
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default:
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break;
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}
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/* unbypass the PLL */
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mmio_clrbits_32(HW_DRAM_PLL_CFG0, 0x30);
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while (!(mmio_read_32(HW_DRAM_PLL_CFG0) & (1 << 31))) {
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;
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}
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}
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#else
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void dram_pll_init(unsigned int drate)
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{
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/* bypass the PLL */
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mmio_setbits_32(DRAM_PLL_CTRL, (1 << 16));
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mmio_clrbits_32(DRAM_PLL_CTRL, (1 << 9));
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switch (drate) {
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case 2400:
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mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (3 << 4) | 2);
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break;
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case 1600:
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mmio_write_32(DRAM_PLL_CTRL + 0x4, (400 << 12) | (3 << 4) | 3);
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break;
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case 1066:
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mmio_write_32(DRAM_PLL_CTRL + 0x4, (266 << 12) | (3 << 4) | 3);
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break;
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case 667:
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mmio_write_32(DRAM_PLL_CTRL + 0x4, (334 << 12) | (3 << 4) | 4);
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break;
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default:
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break;
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}
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mmio_setbits_32(DRAM_PLL_CTRL, BIT(9));
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/* wait for PLL locked */
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while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) {
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;
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}
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/* unbypass the PLL */
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mmio_clrbits_32(DRAM_PLL_CTRL, BIT(16));
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}
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#endif
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/* change the dram clock frequency */
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void dram_clock_switch(unsigned int target_drate, bool bypass_mode)
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{
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if (bypass_mode) {
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switch (target_drate) {
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case 400:
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ddr_pll_bypass_400mts();
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break;
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case 100:
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ddr_pll_bypass_100mts();
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break;
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default:
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ddr_pll_unbypass();
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break;
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}
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} else {
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dram_pll_init(target_drate);
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}
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}
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