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31b3945527
Rename cortex_hunter to cortex_a720 Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
126 lines
3.7 KiB
Makefile
126 lines
3.7 KiB
Makefile
#
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# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include common/fdt_wrappers.mk
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include lib/libfdt/libfdt.mk
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RESET_TO_BL31 := 1
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ifeq (${RESET_TO_BL31}, 0)
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$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
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endif
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ifeq (${ENABLE_PIE}, 1)
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override SEPARATE_CODE_AND_RODATA := 1
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endif
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CTX_INCLUDE_AARCH32_REGS := 0
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ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
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$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
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endif
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ifeq (${TRUSTED_BOARD_BOOT}, 1)
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$(error "TRUSTED_BOARD_BOOT must be disabled")
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endif
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PRELOADED_BL33_BASE := 0x80080000
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FPGA_PRELOADED_DTB_BASE := 0x80070000
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$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
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FPGA_PRELOADED_CMD_LINE := 0x1000
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$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
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ENABLE_FEAT_AMU := 2
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# Treating this as a memory-constrained port for now
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USE_COHERENT_MEM := 0
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# This can be overridden depending on CPU(s) used in the FPGA image
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HW_ASSISTED_COHERENCY := 1
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PL011_GENERIC_UART := 1
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SUPPORT_UNKNOWN_MPID ?= 1
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FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
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# select a different set of CPU files, depending on whether we compile for
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# hardware assisted coherency cores or not
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ifeq (${HW_ASSISTED_COHERENCY}, 0)
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# Cores used without DSU
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/cortex_a73.S
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else
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# AArch64-only cores
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \
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lib/cpus/aarch64/cortex_a710.S \
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lib/cpus/aarch64/cortex_a715.S \
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lib/cpus/aarch64/cortex_a720.S \
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lib/cpus/aarch64/cortex_x3.S \
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lib/cpus/aarch64/cortex_x4.S \
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lib/cpus/aarch64/neoverse_n_common.S \
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lib/cpus/aarch64/neoverse_n1.S \
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lib/cpus/aarch64/neoverse_n2.S \
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lib/cpus/aarch64/neoverse_v1.S \
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lib/cpus/aarch64/cortex_hayes.S \
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lib/cpus/aarch64/cortex_chaberton.S \
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lib/cpus/aarch64/cortex_blackhawk.S
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# AArch64/AArch32 cores
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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lib/cpus/aarch64/cortex_a75.S
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endif
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ifeq (${SUPPORT_UNKNOWN_MPID}, 1)
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# Add support for unknown/invalid MPIDs (aarch64 only)
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$(eval $(call add_define,SUPPORT_UNKNOWN_MPID))
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FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S
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endif
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# Allow detection of GIC-600
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GICV3_SUPPORT_GIC600 := 1
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GIC_ENABLE_V4_EXTN := 1
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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FPGA_GIC_SOURCES := ${GICV3_SOURCES} \
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plat/common/plat_gicv3.c \
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plat/arm/board/arm_fpga/fpga_gicv3.c
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FDT_SOURCES := fdts/arm_fpga.dts
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PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
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PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
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BL31_SOURCES += common/fdt_fixup.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/arm/pl011/${ARCH}/pl011_console.S \
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plat/common/plat_psci_common.c \
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plat/arm/board/arm_fpga/fpga_pm.c \
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plat/arm/board/arm_fpga/fpga_topology.c \
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plat/arm/board/arm_fpga/fpga_console.c \
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plat/arm/board/arm_fpga/fpga_bl31_setup.c \
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${FPGA_CPU_LIBS} \
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${FPGA_GIC_SOURCES}
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BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
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$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,bl31))
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$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/kernel_trampoline.S,bl31))
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$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,bl31))
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bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/kernel_trampoline.o ${BUILD_PLAT}/build_axf.ld
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$(ECHO) " LD $@"
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$(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -s -n -o ${BUILD_PLAT}/bl31.axf
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all: bl31.axf
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