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7db0c96023
PSCI requires a core to turn itself off, which we can't do properly by just executing an algorithm on that very core. As a consequence we just put a core into WFI on CPU_OFF right now. To fix this let's task the "arisc" management processor (an OpenRISC core) with that task of asserting reset and turning off the core's power domain. We use a handcrafted sequence of OpenRISC instructions to achieve this, and hand this data over to the new sunxi_execute_arisc_code() routine. The commented source code for this routine is provided in a separate file, but the ATF code contains the already encoded instructions as data. The H6 uses the same algorithm, but differs in the MMIO addresses, so provide a SoC (family) specific copy of that code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
110 lines
3.5 KiB
C
110 lines
3.5 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <core_off_arisc.h>
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#include <debug.h>
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#include <delay_timer.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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#include <utils_def.h>
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static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
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{
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if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
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return;
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VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff);
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}
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static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
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{
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if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0)
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return;
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VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core);
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/* Power enable sequence from original Allwinner sources */
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
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}
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void sunxi_cpu_off(unsigned int cluster, unsigned int core)
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{
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int corenr = cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core;
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VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
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/* Deassert DBGPWRDUP */
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mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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/* We can't turn ourself off like this, but it works for other cores. */
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if (plat_my_core_pos() != corenr) {
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/* Activate the core output clamps, but not for core 0. */
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if (corenr != 0)
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mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
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BIT(core));
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/* Assert CPU power-on reset */
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mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Remove power from the CPU */
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sunxi_cpu_disable_power(cluster, core);
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return;
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}
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/* Simplifies assembly, all SoCs so far are single cluster anyway. */
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assert(cluster == 0);
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/*
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* If we are supposed to turn ourself off, tell the arisc SCP
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* to do that work for us. The code expects the core mask to be
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* patched into the first instruction.
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*/
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sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
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0, BIT_32(core));
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}
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void sunxi_cpu_on(unsigned int cluster, unsigned int core)
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{
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VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
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/* Assert CPU core reset */
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mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
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/* Assert CPU power-on reset */
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mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Set CPU to start in AArch64 mode */
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mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core));
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/* Apply power to the CPU */
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sunxi_cpu_enable_power(cluster, core);
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/* Release the core output clamps */
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mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
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/* Deassert CPU power-on reset */
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mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Deassert CPU core reset */
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mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
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/* Assert DBGPWRDUP */
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mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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}
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void sunxi_disable_secondary_cpus(unsigned int primary_cpu)
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{
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for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) {
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if (cpu == primary_cpu)
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continue;
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sunxi_cpu_off(cpu / PLATFORM_MAX_CPUS_PER_CLUSTER,
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cpu % PLATFORM_MAX_CPUS_PER_CLUSTER);
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}
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}
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