Soby Mathew 311b177364 Flush the GIC driver data after init ... The GIC driver data is initialized by the primary CPU with caches enabled. When the secondary CPU boots up, it initializes the GICC/GICR interface with the caches disabled and there is a chance that the driver data is not yet written back to the memory. This patch fixes this problem by flushing the driver data after they have been initialized. Change-Id: Ie9477029683846209593ff005d2bac559bb8f5e6 Signed-off-by: Soby Mathew <soby.mathew@arm.com>		2017-03-01 14:38:28 +00:00
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cci	Use uintptr_t as base address type in ARM driver APIs	2015-07-09 11:53:32 +01:00
cci400	Fix debug assertion in deprecated CCI-400 driver	2015-10-12 10:21:55 +01:00
ccn	Use #ifdef for IMAGE_BL* instead of #if	2017-01-24 01:01:21 +09:00
gic	Flush the GIC driver data after init	2017-03-01 14:38:28 +00:00
pl011	AArch32: Miscellaneous fixes in the AArch32 code	2016-12-01 11:02:51 +00:00
pl061	utils: move BIT(n) macro to utils.h	2017-01-13 04:34:24 +09:00
sp804	Add SP804 delay timer driver	2015-06-18 16:06:26 +01:00
sp805	Add a simple ARM SP805 watchdog driver	2015-11-27 09:34:20 +00:00
tzc	AArch32: Enable GIC and TZC support	2016-08-10 12:35:46 +01:00
tzc400	Refactor the ARM CoreLink TZC-400 driver	2016-03-31 21:23:23 +01:00