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https://github.com/ARM-software/arm-trusted-firmware.git
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c703d752cc
SError and Abort are handled in Linux (EL1) instead of EL3. This patch adds some functionality that complements the use cases by Linux as follows: - Provide SMC for ECC DBE notification to EL3 - Determine type of reset needed and service the request in place of Linux Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I43d02c77f28004a31770be53599a5a42de412211
567 lines
13 KiB
C
567 lines
13 KiB
C
/*
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/mmio.h>
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#include <tools_share/uuid.h>
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#include "socfpga_fcs.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_reset_manager.h"
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#include "socfpga_sip_svc.h"
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/* Total buffer the driver can hold */
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#define FPGA_CONFIG_BUFFER_SIZE 4
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static int current_block, current_buffer;
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static int read_block, max_blocks, is_partial_reconfig;
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static uint32_t send_id, rcv_id;
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static uint32_t bytes_per_block, blocks_submitted;
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/* SiP Service UUID */
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DEFINE_SVC_UUID2(intl_svc_uid,
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0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
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0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
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static uint64_t socfpga_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
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static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
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{
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uint32_t args[3];
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while (max_blocks > 0 && buffer->size > buffer->size_written) {
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args[0] = (1<<8);
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args[1] = buffer->addr + buffer->size_written;
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if (buffer->size - buffer->size_written <= bytes_per_block) {
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args[2] = buffer->size - buffer->size_written;
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current_buffer++;
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current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
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} else
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args[2] = bytes_per_block;
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buffer->size_written += args[2];
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mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
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3U, CMD_INDIRECT);
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buffer->subblocks_sent++;
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max_blocks--;
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}
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return !max_blocks;
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}
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static int intel_fpga_sdm_write_all(void)
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{
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for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
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if (intel_fpga_sdm_write_buffer(
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&fpga_config_buffers[current_buffer]))
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break;
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return 0;
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}
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static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type)
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{
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uint32_t ret;
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if (query_type == 1)
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ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false);
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else
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ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true);
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if (ret) {
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if (ret == MBOX_CFGSTAT_STATE_CONFIG)
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return INTEL_SIP_SMC_STATUS_BUSY;
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else
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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if (query_type != 1) {
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/* full reconfiguration */
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if (!is_partial_reconfig)
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socfpga_bridges_enable(); /* Enable bridge */
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}
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
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{
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int i;
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for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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if (fpga_config_buffers[i].block_number == current_block) {
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fpga_config_buffers[i].subblocks_sent--;
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if (fpga_config_buffers[i].subblocks_sent == 0
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&& fpga_config_buffers[i].size <=
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fpga_config_buffers[i].size_written) {
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fpga_config_buffers[i].write_requested = 0;
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current_block++;
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*buffer_addr_completed =
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fpga_config_buffers[i].addr;
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return 0;
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}
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}
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}
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return -1;
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}
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static int intel_fpga_config_completed_write(uint32_t *completed_addr,
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uint32_t *count, uint32_t *job_id)
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{
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uint32_t resp[5];
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unsigned int resp_len = ARRAY_SIZE(resp);
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int status = INTEL_SIP_SMC_STATUS_OK;
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int all_completed = 1;
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*count = 0;
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while (*count < 3) {
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status = mailbox_read_response(job_id,
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resp, &resp_len);
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if (status < 0) {
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break;
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}
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max_blocks++;
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if (mark_last_buffer_xfer_completed(
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&completed_addr[*count]) == 0) {
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*count = *count + 1;
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} else {
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break;
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}
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}
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if (*count <= 0) {
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if (status != MBOX_NO_RESPONSE &&
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status != MBOX_TIMEOUT && resp_len != 0) {
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mailbox_clear_response();
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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*count = 0;
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}
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intel_fpga_sdm_write_all();
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if (*count > 0)
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status = INTEL_SIP_SMC_STATUS_OK;
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else if (*count == 0)
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status = INTEL_SIP_SMC_STATUS_BUSY;
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for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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if (fpga_config_buffers[i].write_requested != 0) {
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all_completed = 0;
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break;
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}
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}
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if (all_completed == 1)
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return INTEL_SIP_SMC_STATUS_OK;
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return status;
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}
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static int intel_fpga_config_start(uint32_t config_type)
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{
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uint32_t argument = 0x1;
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uint32_t response[3];
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int status = 0;
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unsigned int size = 0;
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unsigned int resp_len = ARRAY_SIZE(response);
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is_partial_reconfig = config_type;
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mailbox_clear_response();
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mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
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CMD_CASUAL, NULL, NULL);
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status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
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CMD_CASUAL, response, &resp_len);
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if (status < 0)
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return status;
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max_blocks = response[0];
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bytes_per_block = response[1];
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for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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fpga_config_buffers[i].size = 0;
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fpga_config_buffers[i].size_written = 0;
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fpga_config_buffers[i].addr = 0;
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fpga_config_buffers[i].write_requested = 0;
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fpga_config_buffers[i].block_number = 0;
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fpga_config_buffers[i].subblocks_sent = 0;
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}
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blocks_submitted = 0;
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current_block = 0;
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read_block = 0;
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current_buffer = 0;
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/* full reconfiguration */
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if (!is_partial_reconfig) {
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/* Disable bridge */
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socfpga_bridges_disable();
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}
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return 0;
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}
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static bool is_fpga_config_buffer_full(void)
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{
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for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
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if (!fpga_config_buffers[i].write_requested)
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return false;
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return true;
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}
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bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
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{
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if (!addr && !size) {
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return true;
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}
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if (size > (UINT64_MAX - addr))
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return false;
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if (addr < BL31_LIMIT)
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return false;
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if (addr + size > DRAM_BASE + DRAM_SIZE)
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return false;
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return true;
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}
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static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
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{
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int i;
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intel_fpga_sdm_write_all();
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if (!is_address_in_ddr_range(mem, size) ||
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is_fpga_config_buffer_full())
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return INTEL_SIP_SMC_STATUS_REJECTED;
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for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
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int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
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if (!fpga_config_buffers[j].write_requested) {
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fpga_config_buffers[j].addr = mem;
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fpga_config_buffers[j].size = size;
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fpga_config_buffers[j].size_written = 0;
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fpga_config_buffers[j].write_requested = 1;
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fpga_config_buffers[j].block_number =
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blocks_submitted++;
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fpga_config_buffers[j].subblocks_sent = 0;
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break;
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}
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}
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if (is_fpga_config_buffer_full())
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return INTEL_SIP_SMC_STATUS_BUSY;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static int is_out_of_sec_range(uint64_t reg_addr)
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{
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switch (reg_addr) {
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case(0xF8011100): /* ECCCTRL1 */
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case(0xF8011104): /* ECCCTRL2 */
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case(0xF8011110): /* ERRINTEN */
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case(0xF8011114): /* ERRINTENS */
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case(0xF8011118): /* ERRINTENR */
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case(0xF801111C): /* INTMODE */
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case(0xF8011120): /* INTSTAT */
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case(0xF8011124): /* DIAGINTTEST */
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case(0xF801112C): /* DERRADDRA */
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case(0xFFD12028): /* SDMMCGRP_CTRL */
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case(0xFFD12044): /* EMAC0 */
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case(0xFFD12048): /* EMAC1 */
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case(0xFFD1204C): /* EMAC2 */
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case(0xFFD12090): /* ECC_INT_MASK_VALUE */
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case(0xFFD12094): /* ECC_INT_MASK_SET */
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case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
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case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
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case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
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case(0xFFD120C0): /* NOC_TIMEOUT */
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case(0xFFD120C4): /* NOC_IDLEREQ_SET */
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case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
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case(0xFFD120D0): /* NOC_IDLEACK */
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case(0xFFD120D4): /* NOC_IDLESTATUS */
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case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
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case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
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case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
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case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
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return 0;
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default:
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break;
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}
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return -1;
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}
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/* Secure register access */
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uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
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{
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if (is_out_of_sec_range(reg_addr))
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return INTEL_SIP_SMC_STATUS_ERROR;
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*retval = mmio_read_32(reg_addr);
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return INTEL_SIP_SMC_STATUS_OK;
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}
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uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
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uint32_t *retval)
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{
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if (is_out_of_sec_range(reg_addr))
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return INTEL_SIP_SMC_STATUS_ERROR;
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mmio_write_32(reg_addr, val);
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return intel_secure_reg_read(reg_addr, retval);
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}
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uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
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uint32_t val, uint32_t *retval)
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{
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if (!intel_secure_reg_read(reg_addr, retval)) {
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*retval &= ~mask;
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*retval |= val & mask;
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return intel_secure_reg_write(reg_addr, *retval, retval);
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}
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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/* Intel Remote System Update (RSU) services */
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uint64_t intel_rsu_update_address;
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static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
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{
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if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
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return INTEL_SIP_SMC_RSU_ERROR;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static uint32_t intel_rsu_update(uint64_t update_address)
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{
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intel_rsu_update_address = update_address;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static uint32_t intel_rsu_notify(uint32_t execution_stage)
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{
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if (mailbox_hps_stage_notify(execution_stage) < 0)
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return INTEL_SIP_SMC_RSU_ERROR;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
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uint32_t *ret_stat)
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{
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if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
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return INTEL_SIP_SMC_RSU_ERROR;
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*ret_stat = respbuf[8];
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return INTEL_SIP_SMC_STATUS_OK;
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}
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/* Mailbox services */
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static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
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unsigned int len,
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uint32_t urgent, uint32_t *response,
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unsigned int resp_len, int *mbox_status,
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unsigned int *len_in_resp)
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{
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*len_in_resp = 0;
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*mbox_status = 0;
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if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len))
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return INTEL_SIP_SMC_STATUS_REJECTED;
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int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
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response, &resp_len);
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if (status < 0) {
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*mbox_status = -status;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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*mbox_status = 0;
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*len_in_resp = resp_len;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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/*
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* This function is responsible for handling all SiP calls from the NS world
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*/
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uintptr_t sip_smc_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags)
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{
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uint32_t retval = 0;
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uint32_t completed_addr[3];
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uint64_t rsu_respbuf[9];
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int status = INTEL_SIP_SMC_STATUS_OK;
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int mbox_status;
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unsigned int len_in_resp;
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u_register_t x5, x6;
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switch (smc_fid) {
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case SIP_SVC_UID:
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/* Return UID to the caller */
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SMC_UUID_RET(handle, intl_svc_uid);
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case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
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status = intel_mailbox_fpga_config_isdone(x1);
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SMC_RET4(handle, status, 0, 0, 0);
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case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
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SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
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INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
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INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
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INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
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case INTEL_SIP_SMC_FPGA_CONFIG_START:
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status = intel_fpga_config_start(x1);
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SMC_RET4(handle, status, 0, 0, 0);
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case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
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status = intel_fpga_config_write(x1, x2);
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SMC_RET4(handle, status, 0, 0, 0);
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case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
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status = intel_fpga_config_completed_write(completed_addr,
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&retval, &rcv_id);
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switch (retval) {
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case 1:
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SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
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completed_addr[0], 0, 0);
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case 2:
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SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
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completed_addr[0],
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completed_addr[1], 0);
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case 3:
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SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
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completed_addr[0],
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completed_addr[1],
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completed_addr[2]);
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case 0:
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SMC_RET4(handle, status, 0, 0, 0);
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default:
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mailbox_clear_response();
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SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
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}
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|
case INTEL_SIP_SMC_REG_READ:
|
|
status = intel_secure_reg_read(x1, &retval);
|
|
SMC_RET3(handle, status, retval, x1);
|
|
|
|
case INTEL_SIP_SMC_REG_WRITE:
|
|
status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
|
|
SMC_RET3(handle, status, retval, x1);
|
|
|
|
case INTEL_SIP_SMC_REG_UPDATE:
|
|
status = intel_secure_reg_update(x1, (uint32_t)x2,
|
|
(uint32_t)x3, &retval);
|
|
SMC_RET3(handle, status, retval, x1);
|
|
|
|
case INTEL_SIP_SMC_RSU_STATUS:
|
|
status = intel_rsu_status(rsu_respbuf,
|
|
ARRAY_SIZE(rsu_respbuf));
|
|
if (status) {
|
|
SMC_RET1(handle, status);
|
|
} else {
|
|
SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
|
|
rsu_respbuf[2], rsu_respbuf[3]);
|
|
}
|
|
|
|
case INTEL_SIP_SMC_RSU_UPDATE:
|
|
status = intel_rsu_update(x1);
|
|
SMC_RET1(handle, status);
|
|
|
|
case INTEL_SIP_SMC_RSU_NOTIFY:
|
|
status = intel_rsu_notify(x1);
|
|
SMC_RET1(handle, status);
|
|
|
|
case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
|
|
status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
|
|
ARRAY_SIZE(rsu_respbuf), &retval);
|
|
if (status) {
|
|
SMC_RET1(handle, status);
|
|
} else {
|
|
SMC_RET2(handle, status, retval);
|
|
}
|
|
|
|
case INTEL_SIP_SMC_ECC_DBE:
|
|
status = intel_ecc_dbe_notification(x1);
|
|
SMC_RET1(handle, status);
|
|
|
|
case INTEL_SIP_SMC_MBOX_SEND_CMD:
|
|
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
|
|
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
|
|
status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4,
|
|
(uint32_t *)x5, x6, &mbox_status,
|
|
&len_in_resp);
|
|
SMC_RET3(handle, status, mbox_status, len_in_resp);
|
|
|
|
default:
|
|
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
|
|
cookie, handle, flags);
|
|
}
|
|
}
|
|
|
|
DECLARE_RT_SVC(
|
|
socfpga_sip_svc,
|
|
OEN_SIP_START,
|
|
OEN_SIP_END,
|
|
SMC_TYPE_FAST,
|
|
NULL,
|
|
sip_smc_handler
|
|
);
|
|
|
|
DECLARE_RT_SVC(
|
|
socfpga_sip_svc_std,
|
|
OEN_SIP_START,
|
|
OEN_SIP_END,
|
|
SMC_TYPE_YIELD,
|
|
NULL,
|
|
sip_smc_handler
|
|
);
|