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https://github.com/ARM-software/arm-trusted-firmware.git
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286b96f4bb
This patch adds driver for Intel FPGA's Crypto Services. These services are provided by Intel platform Secure Device Manager(SDM) and are made accessible by processor components (ie ATF). Below is the list of enabled features: - Send SDM certificates - Efuse provision data dump - Encryption/decryption service - Hardware IP random number generator Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: If7604cd1cacf27a38a9a29ec6b85b07385e1ea26
175 lines
5.2 KiB
C
175 lines
5.2 KiB
C
/*
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_MBOX_H
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#define SOCFPGA_MBOX_H
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#include <lib/utils_def.h>
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#define MBOX_OFFSET 0xffa30000
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#define MBOX_ATF_CLIENT_ID 0x1U
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#define MBOX_MAX_JOB_ID 0xFU
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#define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U)
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#define MBOX_JOB_ID MBOX_MAX_JOB_ID
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/* Mailbox Shared Memory Register Map */
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#define MBOX_CIN 0x00
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#define MBOX_ROUT 0x04
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#define MBOX_URG 0x08
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#define MBOX_INT 0x0C
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#define MBOX_COUT 0x20
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#define MBOX_RIN 0x24
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#define MBOX_STATUS 0x2C
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#define MBOX_CMD_BUFFER 0x40
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#define MBOX_RESP_BUFFER 0xC0
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/* Mailbox SDM doorbell */
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#define MBOX_DOORBELL_TO_SDM 0x400
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#define MBOX_DOORBELL_FROM_SDM 0x480
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/* Mailbox commands */
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#define MBOX_CMD_NOOP 0x00
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#define MBOX_CMD_SYNC 0x01
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#define MBOX_CMD_RESTART 0x02
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#define MBOX_CMD_CANCEL 0x03
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#define MBOX_CMD_VAB_SRC_CERT 0x0B
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#define MBOX_CMD_GET_IDCODE 0x10
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#define MBOX_CMD_REBOOT_HPS 0x47
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/* Reconfiguration Commands */
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#define MBOX_CONFIG_STATUS 0x04
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#define MBOX_RECONFIG 0x06
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#define MBOX_RECONFIG_DATA 0x08
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#define MBOX_RECONFIG_STATUS 0x09
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/* QSPI Commands */
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#define MBOX_CMD_QSPI_OPEN 0x32
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#define MBOX_CMD_QSPI_CLOSE 0x33
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#define MBOX_CMD_QSPI_SET_CS 0x34
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#define MBOX_CMD_QSPI_DIRECT 0x3B
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/* RSU Commands */
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#define MBOX_GET_SUBPARTITION_TABLE 0x5A
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#define MBOX_RSU_STATUS 0x5B
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#define MBOX_RSU_UPDATE 0x5C
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#define MBOX_HPS_STAGE_NOTIFY 0x5D
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/* FCS Command */
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#define MBOX_FCS_GET_PROVISION 0x7B
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#define MBOX_FCS_ENCRYPT_REQ 0x7E
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#define MBOX_FCS_DECRYPT_REQ 0x7F
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#define MBOX_FCS_RANDOM_GEN 0x80
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/* Mailbox Definitions */
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#define CMD_DIRECT 0
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#define CMD_INDIRECT 1
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#define CMD_CASUAL 0
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#define CMD_URGENT 1
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#define MBOX_WORD_BYTE 4U
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_CMD_BUFFER_SIZE 32
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/* Execution states for HPS_STAGE_NOTIFY */
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#define HPS_EXECUTION_STATE_FSBL 0
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#define HPS_EXECUTION_STATE_SSBL 1
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#define HPS_EXECUTION_STATE_OS 2
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/* Status Response */
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#define MBOX_RET_OK 0
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#define MBOX_RET_ERROR -1
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#define MBOX_NO_RESPONSE -2
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#define MBOX_WRONG_ID -3
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#define MBOX_BUFFER_FULL -4
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#define MBOX_TIMEOUT -2047
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/* Reconfig Status Response */
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#define RECONFIG_STATUS_STATE 0
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#define RECONFIG_STATUS_PIN_STATUS 2
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#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
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#define PIN_STATUS_NSTATUS (U(1) << 31)
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#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
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#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
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#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
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#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
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#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
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#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
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#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
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#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
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#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
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#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
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#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
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#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
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#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
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#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
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/* Mailbox Macros */
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#define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \
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+ MBOX_WORD_BYTE * (ptr))
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/* Mailbox interrupt flags and masks */
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#define MBOX_INT_FLAG_COE 0x1
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#define MBOX_INT_FLAG_RIE 0x2
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#define MBOX_INT_FLAG_UAE 0x100
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#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
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#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
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/* Mailbox response and status */
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#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff)
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#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
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#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
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#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
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#define MBOX_STATUS_UA_MASK (1<<8)
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/* Mailbox command and response */
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#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
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#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
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#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
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#define MBOX_INDIRECT(val) ((val) << 11)
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#define MBOX_CMD_MASK(header) ((header) & 0x7ff)
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/* RSU Macros */
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#define RSU_VERSION_ACMF BIT(8)
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#define RSU_VERSION_ACMF_MASK 0xff00
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/* Mailbox Function Definitions */
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void mailbox_set_int(uint32_t interrupt_input);
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int mailbox_init(void);
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void mailbox_set_qspi_close(void);
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void mailbox_hps_qspi_enable(void);
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int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
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unsigned int len, uint32_t urgent, uint32_t *response,
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unsigned int *resp_len);
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int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
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unsigned int len, unsigned int indirect);
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int mailbox_read_response(uint32_t *job_id, uint32_t *response,
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unsigned int *resp_len);
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int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
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unsigned int *resp_len);
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void mailbox_reset_cold(void);
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void mailbox_clear_response(void);
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int intel_mailbox_get_config_status(uint32_t cmd, bool init_done);
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int intel_mailbox_is_fpga_not_ready(void);
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int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_update(uint32_t *flash_offset);
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int mailbox_hps_stage_notify(uint32_t execution_stage);
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#endif /* SOCFPGA_MBOX_H */
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