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306551362c
This patch disables trapping to EL3 when the FEAT_D128 specific registers are accessed by setting the SCR_EL3.D128En bit. If FEAT_D128 is implemented, then FEAT_SYSREG128 is implemented. With FEAT_SYSREG128 certain system registers are treated as 128-bit, so we should be context saving and restoring 128-bits instead of 64-bit when FEAT_D128 is enabled. FEAT_SYSREG128 adds support for MRRS and MSRR instruction which helps us to read write to 128-bit system register. Refer to Arm Architecture Manual for further details. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Change-Id: I1a53db5eac29e56c8fbdcd4961ede3abfcb2411a Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
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| .. | ||
| aarch32 | ||
| aarch64 | ||
| backtrace | ||
| bl_common.c | ||
| desc_image_load.c | ||
| fdt_fixup.c | ||
| fdt_wrappers.c | ||
| fdt_wrappers.mk | ||
| feat_detect.c | ||
| image_decompress.c | ||
| runtime_svc.c | ||
| tf_crc32.c | ||
| tf_log.c | ||
| uuid.c | ||