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https://github.com/ARM-software/arm-trusted-firmware.git
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3ca3c27cad
This patch adds support to enter System Suspend on Tegra210 platforms without the traditional BPMP firmware. The BPMP firmware will no longer be supported on Tegra210 platforms and its functionality will be divided across the CPU and sc7entry-fw. The sc7entry-fw takes care of performing the hardware sequence required to enter System Suspend (SC7 power state) from the COP. The CPU is required to load this firmware to the internal RAM of the COP and start the sequence. The CPU also make sure that the COP is off after cold boot and is only powered on when we want to start the actual System Suspend sequence. The previous bootloader loads the firmware to TZDRAM and passes its base and size as part of the boot parameters. The EL3 layer is supposed to sanitize the parameters before touching the firmware blob. To assist the warmboot code with the PMIC discovery, EL3 is also supposed to program PMC's scratch register #210, with appropriate values. Without these settings the warmboot code wont be able to get the device out of System Suspend. Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
322 lines
10 KiB
C
322 lines
10 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <cortex_a53.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <flowctrl.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#include <utils_def.h>
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#define CLK_RST_DEV_L_SET 0x300
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#define CLK_RST_DEV_L_CLR 0x304
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#define CLK_BPMP_RST (1 << 1)
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#define EVP_BPMP_RESET_VECTOR 0x200
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static const uint64_t flowctrl_offset_cpu_csr[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16)
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};
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static const uint64_t flowctrl_offset_halt_cpu[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16)
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};
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static const uint64_t flowctrl_offset_cc4_ctrl[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 12)
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};
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static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]);
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}
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static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]);
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}
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static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]);
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}
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static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr)
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{
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uint32_t val;
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val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ |
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FLOWCTRL_HALT_LIC_IRQ | FLOWCTRL_HALT_LIC_FIQ |
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FLOWCTRL_WAITEVENT;
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tegra_fc_halt_cpu(cpu_id, val);
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val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG |
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FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu_id);
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tegra_fc_cpu_csr(cpu_id, val | csr);
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}
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/*******************************************************************************
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* After this, no core can wake from C7 until the action is reverted.
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* If a wake up event is asserted, the FC state machine will stall until
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* the action is reverted.
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******************************************************************************/
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void tegra_fc_ccplex_pgexit_lock(void)
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{
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unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
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uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;;
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uint32_t icept_cpu_flags[] = {
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INTERCEPT_EXIT_PG_CORE0,
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INTERCEPT_EXIT_PG_CORE1,
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INTERCEPT_EXIT_PG_CORE2,
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INTERCEPT_EXIT_PG_CORE3
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};
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/* set the intercept flags */
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for (i = 0; i < ARRAY_SIZE(icept_cpu_flags); i++) {
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/* skip current CPU */
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if (i == cpu)
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continue;
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/* enable power gate exit intercept locks */
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flags |= icept_cpu_flags[i];
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}
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tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, flags);
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(void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT);
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}
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/*******************************************************************************
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* Revert the ccplex powergate exit locks
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******************************************************************************/
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void tegra_fc_ccplex_pgexit_unlock(void)
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{
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/* clear lock bits, clear pending interrupts */
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tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, INTERCEPT_IRQ_PENDING);
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(void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT);
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}
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/*******************************************************************************
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* Powerdn the current CPU
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******************************************************************************/
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void tegra_fc_cpu_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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VERBOSE("CPU%d powering down...\n", cpu);
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tegra_fc_prepare_suspend(cpu, 0);
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}
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/*******************************************************************************
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* Suspend the current CPU cluster
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******************************************************************************/
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void tegra_fc_cluster_idle(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering cluster idle state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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/* hardware L2 flush is faster for A53 only */
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL,
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!!MPIDR_AFFLVL1_VAL(mpidr));
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/* suspend the CPU cluster */
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val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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}
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/*******************************************************************************
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* Power down the current CPU cluster
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******************************************************************************/
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void tegra_fc_cluster_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering cluster powerdn state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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/* hardware L2 flush is faster for A53 only */
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL,
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read_midr() == CORTEX_A53_MIDR);
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/* power down the CPU cluster */
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val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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}
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/*******************************************************************************
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* Check if cluster idle or power down state is allowed from this CPU
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******************************************************************************/
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bool tegra_fc_is_ccx_allowed(void)
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{
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unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
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uint32_t val;
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bool ccx_allowed = true;
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for (i = 0; i < ARRAY_SIZE(flowctrl_offset_cpu_csr); i++) {
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/* skip current CPU */
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if (i == cpu)
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continue;
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/* check if all other CPUs are already halted */
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val = mmio_read_32(flowctrl_offset_cpu_csr[i]);
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if ((val & FLOWCTRL_CSR_HALT_MASK) == 0U) {
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ccx_allowed = false;
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}
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}
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return ccx_allowed;
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}
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/*******************************************************************************
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* Suspend the entire SoC
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******************************************************************************/
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void tegra_fc_soc_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering SoC powerdn state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 1);
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val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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/* overwrite HALT register */
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT);
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}
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/*******************************************************************************
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* Power up the CPU
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******************************************************************************/
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void tegra_fc_cpu_on(int cpu)
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{
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tegra_fc_cpu_csr(cpu, FLOWCTRL_CSR_ENABLE);
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT | FLOWCTRL_HALT_SCLK);
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}
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/*******************************************************************************
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* Power down the CPU
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******************************************************************************/
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void tegra_fc_cpu_off(int cpu)
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{
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uint32_t val;
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/*
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* Flow controller powers down the CPU during wfi. The CPU would be
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* powered on when it receives any interrupt.
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*/
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val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG |
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FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu);
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tegra_fc_cpu_csr(cpu, val);
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT);
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tegra_fc_cc4_ctrl(cpu, 0);
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}
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/*******************************************************************************
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* Inform the BPMP that we have completed the cluster power up
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******************************************************************************/
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void tegra_fc_lock_active_cluster(void)
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{
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uint32_t val;
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val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL);
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val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK;
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tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val);
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val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL);
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}
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/*******************************************************************************
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* Power ON BPMP processor
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******************************************************************************/
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void tegra_fc_bpmp_on(uint32_t entrypoint)
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{
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/* halt BPMP */
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tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT);
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/* Assert BPMP reset */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST);
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/* Set reset address (stored in PMC_SCRATCH39) */
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mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, entrypoint);
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while (entrypoint != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR))
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; /* wait till value reaches EVP_BPMP_RESET_VECTOR */
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/* Wait for 2us before de-asserting the reset signal. */
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udelay(2);
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/* De-assert BPMP reset */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST);
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/* Un-halt BPMP */
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tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0);
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}
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/*******************************************************************************
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* Power OFF BPMP processor
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******************************************************************************/
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void tegra_fc_bpmp_off(void)
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{
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/* halt BPMP */
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tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT);
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/* Assert BPMP reset */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST);
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/* Clear reset address */
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mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, 0);
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while (0 != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR))
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; /* wait till value reaches EVP_BPMP_RESET_VECTOR */
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}
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/*******************************************************************************
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* Route legacy FIQ to the GICD
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******************************************************************************/
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void tegra_fc_enable_fiq_to_ccplex_routing(void)
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{
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uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
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/* set the bit to pass FIQs to the GICD */
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tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val | FLOWCTRL_FIQ2CCPLEX_ENABLE);
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}
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/*******************************************************************************
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* Disable routing legacy FIQ to the GICD
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******************************************************************************/
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void tegra_fc_disable_fiq_to_ccplex_routing(void)
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{
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uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
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/* clear the bit to pass FIQs to the GICD */
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tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val & ~FLOWCTRL_FIQ2CCPLEX_ENABLE);
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}
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