mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-23 21:44:15 +00:00
2f11d548f2
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
293 lines
8.3 KiB
C
293 lines
8.3 KiB
C
/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <errno.h>
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#include <lib/mmio.h>
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#include "agilex_clock_manager.h"
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#include "agilex_handoff.h"
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static const CLOCK_SOURCE_CONFIG clk_source = {
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/* clk_freq_of_eosc1 */
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(uint32_t) 25000000,
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/* clk_freq_of_f2h_free */
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(uint32_t) 400000000,
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/* clk_freq_of_cb_intosc_ls */
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(uint32_t) 50000000,
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};
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uint32_t wait_pll_lock(void)
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{
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uint32_t data;
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uint32_t count = 0;
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do {
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data = mmio_read_32(CLKMGR_OFFSET + CLKMGR_STAT);
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count++;
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if (count >= 1000)
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return -ETIMEDOUT;
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} while ((CLKMGR_STAT_MAINPLLLOCKED(data) == 0) ||
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(CLKMGR_STAT_PERPLLLOCKED(data) == 0));
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return 0;
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}
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uint32_t wait_fsm(void)
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{
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uint32_t data;
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uint32_t count = 0;
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do {
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data = mmio_read_32(CLKMGR_OFFSET + CLKMGR_STAT);
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count++;
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if (count >= 1000)
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return -ETIMEDOUT;
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} while (CLKMGR_STAT_BUSY(data) == CLKMGR_STAT_BUSY_E_BUSY);
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return 0;
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}
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uint32_t pll_source_sync_config(uint32_t pll_mem_offset)
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{
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uint32_t val = 0;
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uint32_t count = 0;
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uint32_t req_status = 0;
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val = (CLKMGR_MEM_WR | CLKMGR_MEM_REQ |
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CLKMGR_MEM_WDAT << CLKMGR_MEM_WDAT_OFFSET | CLKMGR_MEM_ADDR);
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mmio_write_32(pll_mem_offset, val);
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do {
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req_status = mmio_read_32(pll_mem_offset);
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count++;
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} while ((req_status & CLKMGR_MEM_REQ) && (count < 10));
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if (count >= 100)
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return -ETIMEDOUT;
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return 0;
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}
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uint32_t pll_source_sync_read(uint32_t pll_mem_offset)
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{
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uint32_t val = 0;
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uint32_t rdata = 0;
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uint32_t count = 0;
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uint32_t req_status = 0;
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val = (CLKMGR_MEM_REQ | CLKMGR_MEM_ADDR);
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mmio_write_32(pll_mem_offset, val);
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do {
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req_status = mmio_read_32(pll_mem_offset);
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count++;
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} while ((req_status & CLKMGR_MEM_REQ) && (count < 10));
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if (count >= 100)
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return -ETIMEDOUT;
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rdata = mmio_read_32(pll_mem_offset + 0x4);
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INFO("rdata (%x) = %x\n", pll_mem_offset + 0x4, rdata);
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return 0;
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}
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void config_clkmgr_handoff(handoff *hoff_ptr)
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{
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uint32_t mdiv, mscnt, hscnt;
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uint32_t arefclk_div, drefclk_div;
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/* Bypass all mainpllgrp's clocks */
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0x7);
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wait_fsm();
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/* Bypass all perpllgrp's clocks */
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_BYPASS, 0x7f);
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wait_fsm();
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/* Put both PLL in reset and power down */
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mmio_clrbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
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CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
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mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
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CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
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/* Setup main PLL dividers */
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mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm);
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arefclk_div = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(
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hoff_ptr->main_pll_pllglob);
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drefclk_div = CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(
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hoff_ptr->main_pll_pllglob);
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mscnt = 100 / (mdiv / BIT(drefclk_div));
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if (!mscnt)
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mscnt = 1;
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hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_VCOCALIB,
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CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(hscnt) |
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CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(mscnt));
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV,
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hoff_ptr->main_pll_nocdiv);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
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hoff_ptr->main_pll_pllglob);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_FDBCK,
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hoff_ptr->main_pll_fdbck);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC0,
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hoff_ptr->main_pll_pllc0);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC1,
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hoff_ptr->main_pll_pllc1);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC2,
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hoff_ptr->main_pll_pllc2);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC3,
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hoff_ptr->main_pll_pllc3);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM,
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hoff_ptr->main_pll_pllm);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_MPUCLK,
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hoff_ptr->main_pll_mpuclk);
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCCLK,
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hoff_ptr->main_pll_nocclk);
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/* Setup peripheral PLL dividers */
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mdiv = CLKMGR_PERPLL_PLLM_MDIV(hoff_ptr->per_pll_pllm);
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arefclk_div = CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(
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hoff_ptr->per_pll_pllglob);
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drefclk_div = CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(
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hoff_ptr->per_pll_pllglob);
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mscnt = 100 / (mdiv / BIT(drefclk_div));
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if (!mscnt)
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mscnt = 1;
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hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_VCOCALIB,
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CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(hscnt) |
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CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(mscnt));
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EMACCTL,
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hoff_ptr->per_pll_emacctl);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_GPIODIV,
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CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(
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hoff_ptr->per_pll_gpiodiv));
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
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hoff_ptr->per_pll_pllglob);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_FDBCK,
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hoff_ptr->per_pll_fdbck);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC0,
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hoff_ptr->per_pll_pllc0);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC1,
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hoff_ptr->per_pll_pllc1);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC2,
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hoff_ptr->per_pll_pllc2);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC3,
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hoff_ptr->per_pll_pllc3);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM,
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hoff_ptr->per_pll_pllm);
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/* Take both PLL out of reset and power up */
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mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
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CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
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mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
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CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
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wait_pll_lock();
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pll_source_sync_config(CLKMGR_MAINPLL + CLKMGR_MAINPLL_MEM);
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pll_source_sync_read(CLKMGR_MAINPLL + CLKMGR_MAINPLL_MEM);
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pll_source_sync_config(CLKMGR_PERPLL + CLKMGR_PERPLL_MEM);
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pll_source_sync_read(CLKMGR_PERPLL + CLKMGR_PERPLL_MEM);
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/*Configure Ping Pong counters in altera group */
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mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_EMACACTR,
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hoff_ptr->alt_emacactr);
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mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_EMACBCTR,
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hoff_ptr->alt_emacbctr);
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mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_EMACPTPCTR,
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hoff_ptr->alt_emacptpctr);
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mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_GPIODBCTR,
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hoff_ptr->alt_gpiodbctr);
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mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_SDMMCCTR,
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hoff_ptr->alt_sdmmcctr);
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mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_S2FUSER0CTR,
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hoff_ptr->alt_s2fuser0ctr);
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mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_S2FUSER1CTR,
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hoff_ptr->alt_s2fuser1ctr);
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mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_PSIREFCTR,
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hoff_ptr->alt_psirefctr);
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/* Take all PLLs out of bypass */
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0);
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wait_fsm();
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_BYPASS, 0);
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wait_fsm();
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/* Clear loss lock interrupt status register that */
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/* might be set during configuration */
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mmio_setbits_32(CLKMGR_OFFSET + CLKMGR_INTRCLR,
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CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK |
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CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);
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/* Take all ping pong counters out of reset */
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mmio_clrbits_32(CLKMGR_ALTERA + CLKMGR_ALTERA_EXTCNTRST,
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CLKMGR_ALTERA_EXTCNTRST_RESET);
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/* Set safe mode / out of boot mode */
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mmio_clrbits_32(CLKMGR_OFFSET + CLKMGR_CTRL,
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CLKMGR_CTRL_BOOTMODE_SET_MSK);
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wait_fsm();
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/* Enable mainpllgrp's software-managed clock */
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_EN,
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CLKMGR_MAINPLL_EN_RESET);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN,
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CLKMGR_PERPLL_EN_RESET);
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}
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int get_wdt_clk(handoff *hoff_ptr)
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{
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int main_noc_base_clk, l3_main_free_clk, l4_sys_free_clk;
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int data32, mdiv, arefclkdiv, ref_clk;
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data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB);
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switch (CLKMGR_MAINPLL_PLLGLOB_PSRC(data32)) {
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case CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1:
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ref_clk = clk_source.clk_freq_of_eosc1;
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break;
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case CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC:
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ref_clk = clk_source.clk_freq_of_cb_intosc_ls;
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break;
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case CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S:
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ref_clk = clk_source.clk_freq_of_f2h_free;
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break;
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default:
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ref_clk = 0;
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assert(0);
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break;
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}
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arefclkdiv = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(data32);
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mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm);
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ref_clk = (ref_clk / arefclkdiv) * mdiv;
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main_noc_base_clk = ref_clk / (hoff_ptr->main_pll_pllc1 & 0x7ff);
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l3_main_free_clk = main_noc_base_clk / (hoff_ptr->main_pll_nocclk + 1);
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l4_sys_free_clk = l3_main_free_clk / 4;
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return l4_sys_free_clk;
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}
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