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https://github.com/ARM-software/arm-trusted-firmware.git
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2ed09b1ee2
On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt is not direclty wired to the GICD. It goes to the flow controller instead, for power state management. But the flow controller can route the FIQ to the GICD, as a PPI, which can then get routed to the target CPU. This patch adds routines to enable/disable routing the legacy FIQ used by the watchdog timers, to the GICD. Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
241 lines
7.5 KiB
C
241 lines
7.5 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <cortex_a53.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <flowctrl.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#define CLK_RST_DEV_L_SET 0x300
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#define CLK_RST_DEV_L_CLR 0x304
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#define CLK_BPMP_RST (1 << 1)
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#define EVP_BPMP_RESET_VECTOR 0x200
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static const uint64_t flowctrl_offset_cpu_csr[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16)
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};
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static const uint64_t flowctrl_offset_halt_cpu[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16)
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};
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static const uint64_t flowctrl_offset_cc4_ctrl[4] = {
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 8),
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(TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 12)
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};
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static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]);
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}
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static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]);
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}
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static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val)
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{
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mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val);
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val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]);
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}
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static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr)
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{
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uint32_t val;
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val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ |
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FLOWCTRL_HALT_LIC_IRQ | FLOWCTRL_HALT_LIC_FIQ |
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FLOWCTRL_WAITEVENT;
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tegra_fc_halt_cpu(cpu_id, val);
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val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG |
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FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu_id);
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tegra_fc_cpu_csr(cpu_id, val | csr);
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}
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/*******************************************************************************
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* Powerdn the current CPU
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******************************************************************************/
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void tegra_fc_cpu_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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VERBOSE("CPU%d powering down...\n", cpu);
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tegra_fc_prepare_suspend(cpu, 0);
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}
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/*******************************************************************************
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* Suspend the current CPU cluster
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******************************************************************************/
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void tegra_fc_cluster_idle(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering cluster idle state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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/* hardware L2 flush is faster for A53 only */
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL,
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!!MPIDR_AFFLVL1_VAL(mpidr));
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/* suspend the CPU cluster */
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val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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}
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/*******************************************************************************
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* Power down the current CPU cluster
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******************************************************************************/
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void tegra_fc_cluster_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering cluster powerdn state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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/* hardware L2 flush is faster for A53 only */
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL,
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read_midr() == CORTEX_A53_MIDR);
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/* power down the CPU cluster */
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val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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}
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/*******************************************************************************
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* Suspend the entire SoC
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******************************************************************************/
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void tegra_fc_soc_powerdn(uint32_t mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t val;
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VERBOSE("Entering SoC powerdn state...\n");
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tegra_fc_cc4_ctrl(cpu, 0);
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tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 1);
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val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT;
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tegra_fc_prepare_suspend(cpu, val);
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/* overwrite HALT register */
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT);
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}
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/*******************************************************************************
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* Power up the CPU
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******************************************************************************/
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void tegra_fc_cpu_on(int cpu)
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{
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tegra_fc_cpu_csr(cpu, FLOWCTRL_CSR_ENABLE);
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT | FLOWCTRL_HALT_SCLK);
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}
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/*******************************************************************************
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* Power down the CPU
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******************************************************************************/
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void tegra_fc_cpu_off(int cpu)
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{
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uint32_t val;
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/*
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* Flow controller powers down the CPU during wfi. The CPU would be
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* powered on when it receives any interrupt.
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*/
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val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG |
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FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu);
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tegra_fc_cpu_csr(cpu, val);
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tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT);
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tegra_fc_cc4_ctrl(cpu, 0);
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}
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/*******************************************************************************
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* Inform the BPMP that we have completed the cluster power up
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******************************************************************************/
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void tegra_fc_lock_active_cluster(void)
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{
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uint32_t val;
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val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL);
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val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK;
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tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val);
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val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL);
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}
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/*******************************************************************************
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* Reset BPMP processor
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******************************************************************************/
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void tegra_fc_reset_bpmp(void)
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{
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uint32_t val;
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/* halt BPMP */
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tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT);
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/* Assert BPMP reset */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST);
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/* Restore reset address (stored in PMC_SCRATCH39) */
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val = tegra_pmc_read_32(PMC_SCRATCH39);
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mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, val);
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while (val != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR))
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; /* wait till value reaches EVP_BPMP_RESET_VECTOR */
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/* Wait for 2us before de-asserting the reset signal. */
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udelay(2);
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/* De-assert BPMP reset */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST);
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/* Un-halt BPMP */
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tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0);
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}
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/*******************************************************************************
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* Route legacy FIQ to the GICD
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******************************************************************************/
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void tegra_fc_enable_fiq_to_ccplex_routing(void)
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{
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uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
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/* set the bit to pass FIQs to the GICD */
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tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val | FLOWCTRL_FIQ2CCPLEX_ENABLE);
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}
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/*******************************************************************************
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* Disable routing legacy FIQ to the GICD
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******************************************************************************/
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void tegra_fc_disable_fiq_to_ccplex_routing(void)
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{
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uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
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/* clear the bit to pass FIQs to the GICD */
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tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val & ~FLOWCTRL_FIQ2CCPLEX_ENABLE);
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}
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