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https://github.com/ARM-software/arm-trusted-firmware.git
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9be88e75c1
Add new clock driver for STM32MP13. Split the include file to manage either STM32MP13 or STM32MP15. Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e985 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/*
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* Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/arm/tzc400.h>
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#include <drivers/clk.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <lib/fconf/fconf.h>
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#include <lib/object_pool.h>
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#include <libfdt.h>
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#include <tools_share/firmware_image_package.h>
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#include <platform_def.h>
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#include <stm32mp_fconf_getter.h>
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#define STM32MP_REGION_PARAMS 4
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#define STM32MP_MAX_REGIONS 8
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#define FORCE_SEC_REGION BIT(31)
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static uint32_t nb_regions;
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struct dt_id_attr {
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fdt32_t id_attr[STM32MP_MAX_REGIONS];
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};
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void stm32mp1_arch_security_setup(void)
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{
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#if STM32MP13
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clk_enable(TZC);
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#endif
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#if STM32MP15
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clk_enable(TZC1);
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clk_enable(TZC2);
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#endif
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tzc400_init(STM32MP1_TZC_BASE);
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tzc400_disable_filters();
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/*
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* Region 0 set to cover all DRAM at 0xC000_0000
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* Only secure access is granted in read/write.
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*/
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tzc400_configure_region0(TZC_REGION_S_RDWR, 0);
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tzc400_set_action(TZC_ACTION_ERR);
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tzc400_enable_filters();
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}
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void stm32mp1_security_setup(void)
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{
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uint8_t i;
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assert(nb_regions > 0U);
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tzc400_init(STM32MP1_TZC_BASE);
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tzc400_disable_filters();
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/*
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* Region 0 set to cover all DRAM at 0xC000_0000
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* No access is allowed.
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*/
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tzc400_configure_region0(TZC_REGION_S_NONE, 0);
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for (i = 1U; i <= nb_regions; i++) {
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tzc400_update_filters(i, STM32MP1_FILTER_BIT_ALL);
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}
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tzc400_set_action(TZC_ACTION_INT);
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tzc400_enable_filters();
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}
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static int fconf_populate_stm32mp1_firewall(uintptr_t config)
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{
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int node, len;
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unsigned int i;
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const struct dt_id_attr *conf_list;
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const void *dtb = (const void *)config;
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/* Assert the node offset point to "st,mem-firewall" compatible property */
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const char *compatible_str = "st,mem-firewall";
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node = fdt_node_offset_by_compatible(dtb, -1, compatible_str);
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if (node < 0) {
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ERROR("FCONF: Can't find %s compatible in dtb\n", compatible_str);
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return node;
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}
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conf_list = (const struct dt_id_attr *)fdt_getprop(dtb, node, "memory-ranges", &len);
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if (conf_list == NULL) {
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WARN("FCONF: Read cell failed for %s\n", "memory-ranges");
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return -1;
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}
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/* Locate the memory cells and read all values */
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for (i = 0U; i < (unsigned int)(len / (sizeof(uint32_t) * STM32MP_REGION_PARAMS)); i++) {
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uint32_t base;
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uint32_t size;
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uint32_t sec_attr;
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uint32_t nsaid;
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base = fdt32_to_cpu(conf_list->id_attr[i * STM32MP_REGION_PARAMS]);
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size = fdt32_to_cpu(conf_list->id_attr[i * STM32MP_REGION_PARAMS + 1]);
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sec_attr = fdt32_to_cpu(conf_list->id_attr[i * STM32MP_REGION_PARAMS + 2]);
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nsaid = fdt32_to_cpu(conf_list->id_attr[i * STM32MP_REGION_PARAMS + 3]);
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VERBOSE("FCONF: stm32mp1-firewall cell found with value = 0x%x 0x%x 0x%x 0x%x\n",
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base, size, sec_attr, nsaid);
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nb_regions++;
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/* Configure region but keep disabled for secure access for BL2 load */
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tzc400_configure_region(0U, nb_regions, (unsigned long long)base,
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(unsigned long long)base + size - 1ULL, sec_attr, nsaid);
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}
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/* Force flush as the value will be used cache off */
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flush_dcache_range((uintptr_t)&nb_regions, sizeof(uint32_t));
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return 0;
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}
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FCONF_REGISTER_POPULATOR(FW_CONFIG, stm32mp1_firewall, fconf_populate_stm32mp1_firewall);
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