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f808873372
In the chapter about FEAT_SPE (D16.4 specifically) it is stated that "Sampling is always disabled at EL3". That means that disabling sampling (writing PMBLIMITR_EL1.E to 0) is redundant and can be removed. The only reason we save/restore SPE context is because of that disable, so those can be removed too. There's the issue of draining the profiling buffer though. No new samples will have been generated since entering EL3. However, old samples might still be in-flight. Unless synchronised by a psb csync, those might be affected by our extensive context mutation. Adding a psb in prepare_el3_entry should cater for that. Note that prior to the introduction of root context this was not a problem as context remained unchanged and the hooks took care of the rest. Then, the only time we care about the buffer actually making it to memory is when we exit coherency. On HW_ASSISTED_COHERENCY systems we don't have to do anything, it should be handled for us. Systems without it need a dsb to wait for them to complete. There should be one already in each cpu's powerdown hook which should work. While on the topic of barriers, the esb barrier is no longer used. Remove it. Change-Id: I9736fc7d109702c63e7d403dc9e2a4272828afb2 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
29 lines
547 B
C
29 lines
547 B
C
/*
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* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SPE_H
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#define SPE_H
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#include <stdbool.h>
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#include <context.h>
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#if ENABLE_SPE_FOR_NS
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void spe_enable(cpu_context_t *ctx);
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void spe_disable(cpu_context_t *ctx);
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void spe_init_el2_unused(void);
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#else
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static inline void spe_enable(cpu_context_t *ctx)
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{
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}
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static inline void spe_disable(cpu_context_t *ctx)
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{
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}
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static inline void spe_init_el2_unused(void)
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{
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}
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#endif /* ENABLE_SPE_FOR_NS */
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#endif /* SPE_H */
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