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79629b1a79
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
925 lines
36 KiB
C
925 lines
36 KiB
C
/*
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* Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MNPMUSRAMMSGBLOCK_LPDDR4_H
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#define MNPMUSRAMMSGBLOCK_LPDDR4_H
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/* LPDDR4_1D training firmware message block structure
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*
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* Please refer to the Training Firmware App Note for futher information about
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* the usage for Message Block.
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*/
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struct pmu_smb_ddr_1d {
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uint8_t reserved00; /*
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* Byte offset 0x00, CSR Addr 0x54000, Direction=In
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* reserved00[0:4] RFU, must be zero
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*
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* reserved00[5] = Quick Rd2D during 1D Training
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* 0x1 = Read Deskew will begin by enabling and quickly
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* training the phy's per-lane reference voltages.
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* Training the vrefDACs CSRs will increase the maximum 1D
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* training time by around half a millisecond, but will
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* improve 1D training accuracy on systems with
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* significant voltage-offsets between lane read eyes.
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* 0x0 = Read Deskew will assume the messageblock's
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* phyVref setting is optimal for all lanes.
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*
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* reserved00[6] = Enable High Effort WrDQ1D
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* 0x1 = WrDQ1D will conditionally retry training at
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* several extra RxClkDly Timings. This will increase the
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* maximum 1D training time by up to 4 extra iterations of
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* WrDQ1D. This is only required in systems that suffer
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* from very large, asymmetric eye-collapse when receiving
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* PRBS patterns.
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* 0x0 = WrDQ1D assume rxClkDly values found by SI
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* Friendly RdDqs1D will work for receiving PRBS patterns
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*
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* reserved00[7] = Optimize for the special hard macros in
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* TSMC28.
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* 0x1 = set if the phy being trained was manufactured in
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* any TSMC28 process node.
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* 0x0 = otherwise, when not training a TSMC28 phy, leave
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* this field as 0.
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*/
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uint8_t msgmisc; /*
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* Byte offset 0x01, CSR Addr 0x54000, Direction=In
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* Contains various global options for training.
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*
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* Bit fields:
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*
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* msgmisc[0] MTESTEnable
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* 0x1 = Pulse primary digital test output bump at the end
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* of each major training stage. This enables observation
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* of training stage completion by observing the digital
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* test output.
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* 0x0 = Do not pulse primary digital test output bump
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*
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* msgmisc[1] SimulationOnlyReset
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* 0x1 = Verilog only simulation option to shorten
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* duration of DRAM reset pulse length to 1ns.
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* Must never be set to 1 in silicon.
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* 0x0 = Use reset pulse length specified by JEDEC
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* standard.
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*
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* msgmisc[2] SimulationOnlyTraining
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* 0x1 = Verilog only simulation option to shorten the
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* duration of the training steps by performing fewer
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* iterations.
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* Must never be set to 1 in silicon.
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* 0x0 = Use standard training duration.
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*
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* msgmisc[3] Disable Boot Clock
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* 0x1 = Disable boot frequency clock when initializing
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* DRAM. (not recommended)
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* 0x0 = Use Boot Frequency Clock
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*
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* msgmisc[4] Suppress streaming messages, including
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* assertions, regardless of hdtctrl setting.
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* Stage Completion messages, as well as training completion
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* and error messages are still sent depending on hdtctrl
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* setting.
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*
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* msgmisc[5] PerByteMaxRdLat
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* 0x1 = Each DBYTE will return dfi_rddata_valid at the
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* lowest possible latency. This may result in unaligned
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* data between bytes to be returned to the DFI.
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* 0x0 = Every DBYTE will return dfi_rddata_valid
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* simultaneously. This will ensure that data bytes will
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* return aligned accesses to the DFI.
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*
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* msgmisc[7-6] RFU, must be zero
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*
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* Notes:
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*
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* - SimulationOnlyReset and SimulationOnlyTraining can be
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* used to speed up simulation run times, and must never
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* be used in real silicon. Some VIPs may have checks on
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* DRAM reset parameters that may need to be disabled when
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* using SimulationOnlyReset.
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*/
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uint16_t pmurevision; /*
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* Byte offset 0x02, CSR Addr 0x54001, Direction=Out
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* PMU firmware revision ID
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* After training is run, this address will contain the
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* revision ID of the firmware
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*/
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uint8_t pstate; /*
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* Byte offset 0x04, CSR Addr 0x54002, Direction=In
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* Must be set to the target pstate to be trained
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* 0x0 = pstate 0
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* 0x1 = pstate 1
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* 0x2 = pstate 2
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* 0x3 = pstate 3
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* All other encodings are reserved
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*/
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uint8_t pllbypassen; /*
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* Byte offset 0x05, CSR Addr 0x54002, Direction=In
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* Set according to whether target pstate uses PHY PLL
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* bypass
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* 0x0 = PHY PLL is enabled for target pstate
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* 0x1 = PHY PLL is bypassed for target pstate
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*/
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uint16_t dramfreq; /*
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* Byte offset 0x06, CSR Addr 0x54003, Direction=In
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* DDR data rate for the target pstate in units of MT/s.
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* For example enter 0x0640 for DDR1600.
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*/
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uint8_t dfifreqratio; /*
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* Byte offset 0x08, CSR Addr 0x54004, Direction=In
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* Frequency ratio betwen DfiCtlClk and SDRAM memclk.
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* 0x1 = 1:1
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* 0x2 = 1:2
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* 0x4 = 1:4
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*/
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uint8_t bpznresval; /*
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* Byte offset 0x09, CSR Addr 0x54004, Direction=In
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* Overwrite the value of precision resistor connected to
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* Phy BP_ZN
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* 0x00 = Do not program. Use current CSR value.
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* 0xf0 = 240 Ohm
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* 0x78 = 120 Ohm
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* 0x28 = 40 Ohm
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* All other values are reserved.
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* It is recommended to set this to 0x00.
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*/
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uint8_t phyodtimpedance; /*
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* Byte offset 0x0a, CSR Addr 0x54005, Direction=In
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* Must be programmed to the termination impedance in ohms
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* used by PHY during reads.
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*
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* 0x0 = Firmware skips programming (must be manually
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* programmed by user prior to training start)
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*
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* See PHY databook for legal termination impedance values.
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*
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* For digital simulation, any legal value can be used. For
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* silicon, the users must determine the correct value
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* through SI simulation or other methods.
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*/
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uint8_t phydrvimpedance; /*
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* Byte offset 0x0b, CSR Addr 0x54005, Direction=In
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* Must be programmed to the driver impedance in ohms used
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* by PHY during writes for all DBYTE drivers
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* (DQ/DM/DBI/DQS).
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*
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* 0x0 = Firmware skips programming (must be manually
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* programmed by user prior to training start)
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*
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* See PHY databook for legal R_on driver impedance values.
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*
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* For digital simulation, any value can be used that is not
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* Hi-Z. For silicon, the users must determine the correct
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* value through SI simulation or other methods.
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*/
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uint8_t phyvref; /*
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* Byte offset 0x0c, CSR Addr 0x54006, Direction=In
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* Must be programmed with the Vref level to be used by the
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* PHY during reads
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*
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* The units of this field are a percentage of VDDQ
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* according to the following equation:
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*
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* Receiver Vref = VDDQ*phyvref[6:0]/128
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*
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* For example to set Vref at 0.25*VDDQ, set this field to
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* 0x20.
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*
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* For digital simulation, any legal value can be used. For
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* silicon, the users must calculate the analytical Vref by
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* using the impedances, terminations, and series resistance
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* present in the system.
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*/
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uint8_t lp4misc; /*
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* Byte offset 0x0d, CSR Addr 0x54006, Direction=In
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* Lp4 specific options for training.
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*
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* Bit fields:
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*
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* lp4misc[0] Enable dfi_reset_n
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*
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* 0x0 = (Recommended) PHY internal registers control
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* memreset during training, and also after training.
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* dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
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*
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* 0x1 = Enables dfi_reset_n to control memreset after
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* training. PHY Internal registers control memreset
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* during training only. To ensure that no glitches occur
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* on BP_MEMRESET at the end of training, The MC must
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* drive dfi_reset_n=1'b1 _prior to starting training_
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*
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* lp4misc[7-1] RFU, must be zero
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*/
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uint8_t reserved0e; /*
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* Byte offset 0x0e, CSR Addr 0x54007, Direction=In
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* Bit Field for enabling optional 2D training features
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* that impact both Rx2D and Tx2D.
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*
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* reserved0E[0:3]: bitTimeControl
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* input for the amount of data bits 2D writes/reads per DQ
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* before deciding if any specific voltage and delay setting
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* passes or fails. Every time this input increases by 1,
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* the number of 2D data comparisons is doubled. The 2D run
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* time will increase proportionally to the number of bit
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* times requested per point.
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* 0 = 288 bits per point (legacy behavior)
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* 1 = 576 bits per point
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* 2 = 1.125 kilobits per point
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* . . .
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* 15 = 9 megabits per point
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*
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* reserved0E[4]: Exhaustive2D
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* 0 = 2D optimization assumes the optimal trained point
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* is near the 1D trained point (legacy behavior)
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* 1 = 2D optimization searches the entire passing region
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* at the cost of run time. Recommended for optimal
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* results any time the optimal trained point is expected
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* to be near the edges of the eyes instead of near the 1D
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* trained point.
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*
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* reserved0E[5]: Detect Vref Eye Truncation, ignored if
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* eyeWeight2DControl == 0.
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* 0 = 2D optimizes for the passing region it can measure.
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* 1 = For every eye, 2D checks If the legal voltage range
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* truncated the eye. If the true voltage margin cannot be
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* measured, 2D will optimize heavily for delay margin
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* instead of using incomplete voltage margin data. Eyes
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* that are not truncated will still be optimized using
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* user programmed weights.
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*
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* reserved0E[6]: eyeWeight2DControl
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* 0 = Use 8 bit weights for Delay_Weight2D and
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* Voltage_Weight2D and disable TrunkV behavior.
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* 1 = Use 4 bit weights for Delay_weight2D and
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* Voltage_Weight2D and enable TrunkV behavior.
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*
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* reserved0E[7]: RFU, must be 0
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*/
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uint8_t cstestfail; /*
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* Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
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* This field will be set if training fails on any rank.
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* 0x0 = No failures
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* non-zero = one or more ranks failed training
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*/
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uint16_t sequencectrl; /*
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* Byte offset 0x10, CSR Addr 0x54008, Direction=In
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* Controls the training steps to be run. Each bit
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* corresponds to a training step.
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*
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* If the bit is set to 1, the training step will run.
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* If the bit is set to 0, the training step will be
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* skipped.
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*
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* Training step to bit mapping:
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* sequencectrl[0] = Run DevInit - Device/phy
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* initialization. Should always be set.
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* sequencectrl[1] = Run WrLvl - Write leveling
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* sequencectrl[2] = Run RxEn - Read gate training
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* sequencectrl[3] = Run RdDQS1D - 1d read dqs training
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* sequencectrl[4] = Run WrDQ1D - 1d write dq training
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* sequencectrl[5] = RFU, must be zero
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* sequencectrl[6] = RFU, must be zero
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* sequencectrl[7] = RFU, must be zero
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* sequencectrl[8] = Run RdDeskew - Per lane read dq deskew
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* training
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* sequencectrl[9] = Run MxRdLat - Max read latency training
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* sequencectrl[11-10] = RFU, must be zero
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* sequencectrl[12] = Run LPCA - CA Training
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* sequencectrl[15-13] = RFU, must be zero
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*/
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uint8_t hdtctrl; /*
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* Byte offset 0x12, CSR Addr 0x54009, Direction=In
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* To control the total number of debug messages, a
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* verbosity subfield (hdtctrl, Hardware Debug Trace
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* Control) exists in the message block. Every message has a
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* verbosity level associated with it, and as the hdtctrl
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* value is increased, less important s messages stop being
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* sent through the mailboxes. The meanings of several major
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* hdtctrl thresholds are explained below:
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*
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* 0x04 = Maximal debug messages (e.g., Eye contours)
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* 0x05 = Detailed debug messages (e.g. Eye delays)
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* 0x0A = Coarse debug messages (e.g. rank information)
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* 0xC8 = Stage completion
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* 0xC9 = Assertion messages
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* 0xFF = Firmware completion messages only
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*/
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uint8_t reserved13; /*
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* Byte offset 0x13, CSR Addr 0x54009, Direction=In
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*
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* 0 = Default operation, unchanged.
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* Others = RD DQ calibration Training steps are completed
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* with user specified pattern.
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*/
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uint8_t reserved14; /*
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* Byte offset 0x14, CSR Addr 0x5400a, Direction=In
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* Configure rd2D search iteration from a starting seed
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* point:
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*
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* reserved14[5:0]: If reserved14[6] is 0, Number of search
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* iterations (if 0, then default is 20); otherwise if this
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* value non zero, this value is used as a delta to filter
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* out points during the averaging: when averaging over a
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* dimension (delay or voltage), the points having a margin
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* smaller than the max of the eye in this dimension by at
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* least this delta value are filtered out.
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*
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* reserved14[6]: If set, instead of search, extract center
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* using an averaging function over the eye surface area,
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* where some points can be filtered out using
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* reserved14[5:0]
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*
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* reserved14[7]: if set, start search with large step size,
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* decreasing at each 4 iterations, down to 1 (do not care
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* if reserved14[6] is set)
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*/
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uint8_t reserved15; /*
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* Byte offset 0x15, CSR Addr 0x5400a, Direction=In
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* Configure wr2D search iteration from a starting seed
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* point:
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*
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* reserved15[5:0]: If reserved15[6] is 0, Number of search
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* iterations (if 0, then default is 20); otherwise if this
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* value non zero, this value is used as a delta to filter
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* out points during the averaging: when averaging over a
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* dimension (delay or voltage), the points having a margin
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* smaller than the max of the eye in this dimension by at
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* least this delta value are filtered out.
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*
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* reserved15[6]: If set, instead of search, extract center
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* using an averaging function over the eye surface area,
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* where some points can be filtered out using
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* reserved15[5:0]
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*
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* reserved15[7]: if set, start search with large step size,
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* decreasing at each 4 iterations, down to 1 (do not care
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* if reserved15[6] is set)
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*/
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uint8_t dfimrlmargin; /*
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* Byte offset 0x16, CSR Addr 0x5400b, Direction=In
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* Margin added to smallest passing trained DFI Max Read
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* Latency value, in units of DFI clocks. Recommended to be
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* >= 1.
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*
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* This margin must include the maximum positive drift
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* expected in tDQSCK over the target temperature and
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* voltage range of the users system.
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*/
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uint8_t reserved17; /*
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* Byte offset 0x17, CSR Addr 0x5400b, Direction=In
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* Configure DB from which extra info is dump during 2D
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* training when maximal debug is set:
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*
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* reserved17[3:0]: first DB
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*
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* reserved17[7:4]: number of DB, including first DB (if 0,
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* no extra debug per DB is dump)
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*/
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uint8_t usebroadcastmr; /*
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* Byte offset 0x18, CSR Addr 0x5400c, Direction=In
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* Training firmware can optionally set per rank mode
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* register values for DRAM partial array self-refresh
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* features if desired.
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*
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* 0x0 = Use mr<1:4, 11:14, 16:17, 22, 24>_a0 for rank 0
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* channel A
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* Use mr<1:4, 11:14, 16:17, 22, 24>_b0 for rank 0
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* channel B
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* Use mr<1:4, 11:14, 16:17, 22, 24>_a1 for rank 1
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* channel A
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* Use mr<1:4, 11:14, 16:17, 22, 24>_b1 for rank 1
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* channel B
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*
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* 0x1 = Use mr<1:4, 11:14, 16:17, 22, 24>_a0 setting for
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* all channels/ranks
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*
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* It is recommended in most LPDDR4 system configurations
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* to set this to 1.
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* It is recommended in LPDDR4x system configurations to
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* set this to 0.
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*/
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uint8_t lp4quickboot; /*
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* Byte offset 0x19, CSR Addr 0x5400c, Direction=In
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* Enable Quickboot. It must be set to 0x0 since Quickboot
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* is only supported in dedicated Quickboot firmware.
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*/
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uint8_t reserved1a; /*
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* Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
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* Input for constraining the range of vref(DQ) values
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* training will collect data for, usually reducing training
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* time. However, too large of a voltage range may cause
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* longer 2D training times while too small of a voltage
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* range may truncate passing regions. When in doubt, leave
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* this field set to 0.
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* Used by 2D stages: Rd2D, Wr2D
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*
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* reserved1A[0-3]: Rd2D Voltage Range
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* 0 = Training will search all phy vref(DQ) settings
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* 1 = limit to +/-2 %VDDQ from phyVref
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* 2 = limit to +/-4 %VDDQ from phyVref
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* . . .
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* 15 = limit to +/-30% VDDQ from phyVref
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*
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* reserved1A[4-7]: Wr2D Voltage Range
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* 0 = Training will search all dram vref(DQ) settings
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* 1 = limit to +/-2 %VDDQ from mr14
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* 2 = limit to +/-4 %VDDQ from mr14
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* . . .
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* 15 = limit to +/-30% VDDQ from mr14
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*/
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uint8_t catrainopt; /*
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* Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
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* CA training option bit field
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* [0] CA VREF Training
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* 1 = Enable CA VREF Training
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* 0 = Disable CA VREF Training
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* WARNING: catrainopt[0] must be set to the same value in
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* 1D and 2D training.
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*
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* [1] Train terminated Rank only
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* 1 = Only train terminated rank in CA training
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* 0 = Train all ranks in CA training
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*
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* [2-7] RFU must be zero
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*/
|
|
uint8_t x8mode; /*
|
|
* Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
|
|
* X8 mode configuration:
|
|
* 0x0 = x16 configuration for all devices
|
|
* 0xF = x8 configuration for all devices
|
|
* All other values are RFU
|
|
*/
|
|
uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */
|
|
uint8_t reserved1e; /* Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A */
|
|
uint8_t share2dvrefresult; /*
|
|
* Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
|
|
* Bitmap that designates the phy's vref source for every
|
|
* pstate
|
|
* If share2dvrefresult[x] = 0, then after 2D training,
|
|
* pstate x will continue using the phyVref provided in
|
|
* pstate x's 1D messageblock.
|
|
* If share2dvrefresult[x] = 1, then after 2D training,
|
|
* pstate x will use the per-lane VrefDAC0/1 CSRs trained by
|
|
* 2d training.
|
|
*/
|
|
uint8_t reserved20; /* Byte offset 0x20, CSR Addr 0x54010, Direction=N/A */
|
|
uint8_t reserved21; /* Byte offset 0x21, CSR Addr 0x54010, Direction=N/A */
|
|
uint16_t phyconfigoverride; /*
|
|
* Byte offset 0x22, CSR Addr 0x54011, Direction=In
|
|
* Override PhyConfig csr.
|
|
* 0x0: Use hardware csr value for PhyConfing
|
|
* (recommended)
|
|
* Other values: Use value for PhyConfig instead of
|
|
* Hardware value.
|
|
*
|
|
*/
|
|
uint8_t enableddqscha; /*
|
|
* Byte offset 0x24, CSR Addr 0x54012, Direction=In
|
|
* Total number of DQ bits enabled in PHY Channel A
|
|
*/
|
|
uint8_t cspresentcha; /*
|
|
* Byte offset 0x25, CSR Addr 0x54012, Direction=In
|
|
* Indicates presence of DRAM at each chip select for PHY
|
|
* channel A.
|
|
* 0x1 = CS0 is populated with DRAM
|
|
* 0x3 = CS0 and CS1 are populated with DRAM
|
|
*
|
|
* All other encodings are illegal
|
|
*/
|
|
int8_t cdd_cha_rr_1_0; /*
|
|
* Byte offset 0x26, CSR Addr 0x54013, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to read critical delay difference from cs 1 to cs 0
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_rr_0_1; /*
|
|
* Byte offset 0x27, CSR Addr 0x54013, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to read critical delay difference from cs 0 to cs 1
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_rw_1_1; /*
|
|
* Byte offset 0x28, CSR Addr 0x54014, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to write critical delay difference from cs 1 to cs 1
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_rw_1_0; /*
|
|
* Byte offset 0x29, CSR Addr 0x54014, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to write critical delay difference from cs 1 to cs 0
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_rw_0_1; /*
|
|
* Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to write critical delay difference from cs 0 to cs 1
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_rw_0_0; /*
|
|
* Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to write critical delay difference from cs0 to cs 0
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_wr_1_1; /*
|
|
* Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to read critical delay difference from cs 1 to cs 1
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_wr_1_0; /*
|
|
* Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to read critical delay difference from cs 1 to cs 0
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_wr_0_1; /*
|
|
* Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to read critical delay difference from cs 0 to cs 1
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_wr_0_0; /*
|
|
* Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to read critical delay difference from cs 0 to cs 0
|
|
* on Channel A.
|
|
*/
|
|
int8_t cdd_cha_ww_1_0; /*
|
|
* Byte offset 0x30, CSR Addr 0x54018, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to write critical delay difference from cs 1 to cs
|
|
* 0 on Channel A.
|
|
*/
|
|
int8_t cdd_cha_ww_0_1; /*
|
|
* Byte offset 0x31, CSR Addr 0x54018, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to write critical delay difference from cs 0 to cs
|
|
* 1 on Channel A.
|
|
*/
|
|
uint8_t mr1_a0; /*
|
|
* Byte offset 0x32, CSR Addr 0x54019, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 1
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr2_a0; /*
|
|
* Byte offset 0x33, CSR Addr 0x54019, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 2
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr3_a0; /*
|
|
* Byte offset 0x34, CSR Addr 0x5401a, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 3
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr4_a0; /*
|
|
* Byte offset 0x35, CSR Addr 0x5401a, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 4
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr11_a0; /*
|
|
* Byte offset 0x36, CSR Addr 0x5401b, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 11
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr12_a0; /*
|
|
* Byte offset 0x37, CSR Addr 0x5401b, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 12
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr13_a0; /*
|
|
* Byte offset 0x38, CSR Addr 0x5401c, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 13
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr14_a0; /*
|
|
* Byte offset 0x39, CSR Addr 0x5401c, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 14
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr16_a0; /*
|
|
* Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 16
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr17_a0; /*
|
|
* Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 17
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr22_a0; /*
|
|
* Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 22
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr24_a0; /*
|
|
* Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 24
|
|
* {Channel A, Rank 0}
|
|
*/
|
|
uint8_t mr1_a1; /*
|
|
* Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 1
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr2_a1; /*
|
|
* Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 2
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr3_a1; /*
|
|
* Byte offset 0x40, CSR Addr 0x54020, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 3
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr4_a1; /*
|
|
* Byte offset 0x41, CSR Addr 0x54020, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 4
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr11_a1; /*
|
|
* Byte offset 0x42, CSR Addr 0x54021, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 11
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr12_a1; /*
|
|
* Byte offset 0x43, CSR Addr 0x54021, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 12
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr13_a1; /*
|
|
* Byte offset 0x44, CSR Addr 0x54022, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 13
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr14_a1; /*
|
|
* Byte offset 0x45, CSR Addr 0x54022, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 14
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr16_a1; /*
|
|
* Byte offset 0x46, CSR Addr 0x54023, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 16
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr17_a1; /*
|
|
* Byte offset 0x47, CSR Addr 0x54023, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 17
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr22_a1; /*
|
|
* Byte offset 0x48, CSR Addr 0x54024, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 22
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t mr24_a1; /*
|
|
* Byte offset 0x49, CSR Addr 0x54024, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 24
|
|
* {Channel A, Rank 1}
|
|
*/
|
|
uint8_t caterminatingrankcha; /* Byte offset 0x4a, CSR Addr 0x54025, Direction=In
|
|
* Terminating Rank for CA bus on Channel A
|
|
* 0x0 = Rank 0 is terminating rank
|
|
* 0x1 = Rank 1 is terminating rank
|
|
*/
|
|
uint8_t reserved4b; /* Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A */
|
|
uint8_t reserved4c; /* Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A */
|
|
uint8_t reserved4d; /* Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A */
|
|
uint8_t reserved4e; /* Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A */
|
|
uint8_t reserved4f; /* Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A */
|
|
uint8_t reserved50; /* Byte offset 0x50, CSR Addr 0x54028, Direction=N/A */
|
|
uint8_t reserved51; /* Byte offset 0x51, CSR Addr 0x54028, Direction=N/A */
|
|
uint8_t reserved52; /* Byte offset 0x52, CSR Addr 0x54029, Direction=N/A */
|
|
uint8_t reserved53; /* Byte offset 0x53, CSR Addr 0x54029, Direction=N/A */
|
|
uint8_t reserved54; /* Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A */
|
|
uint8_t reserved55; /* Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A */
|
|
uint8_t reserved56; /* Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A */
|
|
uint8_t enableddqschb; /*
|
|
* Byte offset 0x57, CSR Addr 0x5402b, Direction=In
|
|
* Total number of DQ bits enabled in PHY Channel B
|
|
*/
|
|
uint8_t cspresentchb; /*
|
|
* Byte offset 0x58, CSR Addr 0x5402c, Direction=In
|
|
* Indicates presence of DRAM at each chip select for PHY
|
|
* channel B.
|
|
* 0x0 = No chip selects are populated with DRAM
|
|
* 0x1 = CS0 is populated with DRAM
|
|
* 0x3 = CS0 and CS1 are populated with DRAM
|
|
*
|
|
* All other encodings are illegal
|
|
*/
|
|
int8_t cdd_chb_rr_1_0; /*
|
|
* Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to read critical delay difference from cs 1 to cs 0
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_rr_0_1; /*
|
|
* Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to read critical delay difference from cs 0 to cs 1
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_rw_1_1; /*
|
|
* Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to write critical delay difference from cs 1 to cs 1
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_rw_1_0; /*
|
|
* Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to write critical delay difference from cs 1 to cs 0
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_rw_0_1; /*
|
|
* Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to write critical delay difference from cs 0 to cs 1
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_rw_0_0; /*
|
|
* Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
|
|
* This is a signed integer value.
|
|
* Read to write critical delay difference from cs01 to cs 0
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_wr_1_1; /*
|
|
* Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to read critical delay difference from cs 1 to cs 1
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_wr_1_0; /*
|
|
* Byte offset 0x60, CSR Addr 0x54030, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to read critical delay difference from cs 1 to cs 0
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_wr_0_1; /*
|
|
* Byte offset 0x61, CSR Addr 0x54030, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to read critical delay difference from cs 0 to cs 1
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_wr_0_0; /*
|
|
* Byte offset 0x62, CSR Addr 0x54031, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to read critical delay difference from cs 0 to cs 0
|
|
* on Channel B.
|
|
*/
|
|
int8_t cdd_chb_ww_1_0; /*
|
|
* Byte offset 0x63, CSR Addr 0x54031, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to write critical delay difference from cs 1 to cs
|
|
* 0 on Channel B.
|
|
*/
|
|
int8_t cdd_chb_ww_0_1; /*
|
|
* Byte offset 0x64, CSR Addr 0x54032, Direction=Out
|
|
* This is a signed integer value.
|
|
* Write to write critical delay difference from cs 0 to cs
|
|
* 1 on Channel B.
|
|
*/
|
|
uint8_t mr1_b0; /*
|
|
* Byte offset 0x65, CSR Addr 0x54032, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 1
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr2_b0; /*
|
|
* Byte offset 0x66, CSR Addr 0x54033, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 2
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr3_b0; /*
|
|
* Byte offset 0x67, CSR Addr 0x54033, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 3
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr4_b0; /*
|
|
* Byte offset 0x68, CSR Addr 0x54034, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 4
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr11_b0; /*
|
|
* Byte offset 0x69, CSR Addr 0x54034, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 11
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr12_b0; /*
|
|
* Byte offset 0x6a, CSR Addr 0x54035, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 12
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr13_b0; /*
|
|
* Byte offset 0x6b, CSR Addr 0x54035, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 13
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr14_b0; /*
|
|
* Byte offset 0x6c, CSR Addr 0x54036, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 14
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr16_b0; /*
|
|
* Byte offset 0x6d, CSR Addr 0x54036, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 16
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr17_b0; /*
|
|
* Byte offset 0x6e, CSR Addr 0x54037, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 17
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr22_b0; /*
|
|
* Byte offset 0x6f, CSR Addr 0x54037, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 22
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr24_b0; /*
|
|
* Byte offset 0x70, CSR Addr 0x54038, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 24
|
|
* {Channel B, Rank 0}
|
|
*/
|
|
uint8_t mr1_b1; /*
|
|
* Byte offset 0x71, CSR Addr 0x54038, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 1
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr2_b1; /*
|
|
* Byte offset 0x72, CSR Addr 0x54039, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 2
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr3_b1; /*
|
|
* Byte offset 0x73, CSR Addr 0x54039, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 3
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr4_b1; /*
|
|
* Byte offset 0x74, CSR Addr 0x5403a, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 4
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr11_b1; /*
|
|
* Byte offset 0x75, CSR Addr 0x5403a, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 11
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr12_b1; /*
|
|
* Byte offset 0x76, CSR Addr 0x5403b, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 12
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr13_b1; /*
|
|
* Byte offset 0x77, CSR Addr 0x5403b, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 13
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr14_b1; /*
|
|
* Byte offset 0x78, CSR Addr 0x5403c, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 14
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr16_b1; /*
|
|
* Byte offset 0x79, CSR Addr 0x5403c, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 16
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr17_b1; /*
|
|
* Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 17
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr22_b1; /*
|
|
* Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 22
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t mr24_b1; /*
|
|
* Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
|
|
* Value to be programmed in DRAM Mode Register 24
|
|
* {Channel B, Rank 1}
|
|
*/
|
|
uint8_t caterminatingrankchb; /* Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
|
|
* Terminating Rank for CA bus on Channel B
|
|
* 0x0 = Rank 0 is terminating rank
|
|
* 0x1 = Rank 1 is terminating rank
|
|
*/
|
|
uint8_t reserved7e; /* Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A */
|
|
uint8_t reserved7f; /* Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A */
|
|
uint8_t reserved80; /* Byte offset 0x80, CSR Addr 0x54040, Direction=N/A */
|
|
uint8_t reserved81; /* Byte offset 0x81, CSR Addr 0x54040, Direction=N/A */
|
|
uint8_t reserved82; /* Byte offset 0x82, CSR Addr 0x54041, Direction=N/A */
|
|
uint8_t reserved83; /* Byte offset 0x83, CSR Addr 0x54041, Direction=N/A */
|
|
uint8_t reserved84; /* Byte offset 0x84, CSR Addr 0x54042, Direction=N/A */
|
|
uint8_t reserved85; /* Byte offset 0x85, CSR Addr 0x54042, Direction=N/A */
|
|
uint8_t reserved86; /* Byte offset 0x86, CSR Addr 0x54043, Direction=N/A */
|
|
uint8_t reserved87; /* Byte offset 0x87, CSR Addr 0x54043, Direction=N/A */
|
|
uint8_t reserved88; /* Byte offset 0x88, CSR Addr 0x54044, Direction=N/A */
|
|
uint8_t reserved89; /* Byte offset 0x89, CSR Addr 0x54044, Direction=N/A */
|
|
} __packed __aligned(2);
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|
|
|
#endif /* MNPMUSRAMMSGBLOCK_LPDDR4_H */
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