mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 10:04:26 +00:00
2d7b9e5e7f
The current SPM is a prototype that only supports one secure partition in EL0. The objective of SPM is to have multiple partitions. The current MM interface isn't adequate for this, so it is needed to modify heavily the code to add proper support for it. However, there are platforms which are already using this (like SGI) and removing the code would break it. For this reason, the current SPM code has been duplicated in order to temporarily preserve compatibility. All new improvements/changes to SPM will be done in the non-deprecated copy, that may change without notice. The new build option SPM_DEPRECATED has been introduced to select the SPM implementation. It defaults to 1, that selects the deprecated SPM. Change-Id: Ic9f80b53b450e97b4d3f47e4ef4a138ee8d87443 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
128 lines
3.1 KiB
ArmAsm
128 lines
3.1 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <context.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by the spm shim layer.
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* -----------------------------------------------------------------------------
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*/
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.globl spm_shim_exceptions_ptr
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vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSP0, .spm_shim_exceptions
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b .
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end_vector_entry SynchronousExceptionSP0
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vector_entry IrqSP0, .spm_shim_exceptions
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b .
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end_vector_entry IrqSP0
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vector_entry FiqSP0, .spm_shim_exceptions
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b .
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end_vector_entry FiqSP0
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vector_entry SErrorSP0, .spm_shim_exceptions
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b .
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end_vector_entry SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSPx, .spm_shim_exceptions
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b .
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end_vector_entry SynchronousExceptionSPx
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vector_entry IrqSPx, .spm_shim_exceptions
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b .
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end_vector_entry IrqSPx
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vector_entry FiqSPx, .spm_shim_exceptions
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b .
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end_vector_entry FiqSPx
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vector_entry SErrorSPx, .spm_shim_exceptions
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b .
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end_vector_entry SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
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* are handled since secure_partition does not implement
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* a lower EL
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA64, .spm_shim_exceptions
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msr tpidr_el1, x30
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mrs x30, esr_el1
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x30, #EC_AARCH64_SVC
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b.eq do_smc
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cmp x30, #EC_AARCH32_SVC
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b.eq do_smc
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cmp x30, #EC_AARCH64_SYS
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b.eq handle_sys_trap
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/* Fail in all the other cases */
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b panic
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/* ---------------------------------------------
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* Tell SPM that we are done initialising
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* ---------------------------------------------
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*/
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do_smc:
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mrs x30, tpidr_el1
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smc #0
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eret
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/* AArch64 system instructions trap are handled as a panic for now */
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handle_sys_trap:
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panic:
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b panic
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end_vector_entry SynchronousExceptionA64
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vector_entry IrqA64, .spm_shim_exceptions
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b .
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end_vector_entry IrqA64
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vector_entry FiqA64, .spm_shim_exceptions
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b .
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end_vector_entry FiqA64
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vector_entry SErrorA64, .spm_shim_exceptions
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b .
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end_vector_entry SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA32, .spm_shim_exceptions
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b .
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end_vector_entry SynchronousExceptionA32
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vector_entry IrqA32, .spm_shim_exceptions
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b .
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end_vector_entry IrqA32
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vector_entry FiqA32, .spm_shim_exceptions
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b .
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end_vector_entry FiqA32
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vector_entry SErrorA32, .spm_shim_exceptions
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b .
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end_vector_entry SErrorA32
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