Jit Loon Lim 7931d3322d feat(intel): platform enablement for Agilex5 SoC FPGA ... This patch is used to enable platform enablement for Agilex5 SoC FPGA. New feature: 1. Added ATF->Zephyr boot option 2. Added xlat_v2 for MMU 3. Added ATF->Linux boot option 4. Added SMP support 5. Added HPS bridges support 6. Added EMULATOR support 7. Added DDR support 8. Added GICv3 Redistirbution init 9. Added SDMMC/NAND/Combo Phy support 10. Updated GIC as secure access 11. Added CCU driver support 12. Updated product name -> Agilex5 13. Updated register address based on y22ww52.2 RTL 14. Updated system counter freq to 400MHz Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009		2023-07-05 10:11:22 +08:00
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plat_macros.S	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00
platform_def.h	feat(intel): platform enablement for Agilex5 SoC FPGA	2023-07-05 10:11:22 +08:00
socfpga_emac.h	intel: Enable EMAC PHY in Intel FPGA platform	2020-02-25 10:19:51 +08:00
socfpga_f2sdram_manager.h	feat(intel): reset manager support for Agilex5 SoC FPGA	2023-07-05 09:08:31 +08:00
socfpga_fcs.h	fix(intel): update checking for memcpy and memset	2023-05-23 21:09:01 +08:00
socfpga_handoff.h	feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA	2023-07-05 09:08:13 +08:00
socfpga_mailbox.h	feat(intel): mailbox and SMC support for Agilex5 SoC FPGA	2023-07-05 09:08:29 +08:00
socfpga_noc.h	feat(intel): platform enablement for Agilex5 SoC FPGA	2023-07-05 10:11:22 +08:00
socfpga_private.h	feat(intel): implement timer init divider via cpu frequency. (#1)	2022-05-06 17:37:45 +02:00
socfpga_reset_manager.h	feat(intel): reset manager support for Agilex5 SoC FPGA	2023-07-05 09:08:31 +08:00
socfpga_sip_svc.h	feat(intel): add intel_rsu_update() to sip_svc_v2	2023-06-13 15:44:26 +08:00
socfpga_system_manager.h	feat(intel): system manager support for Agilex5 SoC FPGA	2023-07-05 09:08:27 +08:00
socfpga_vab.h	feat(intel): vab support for Agilex5 SoC FPGA	2023-07-05 10:11:18 +08:00