mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
2bd3b39767
This function doesn't return and its callers that don't return either rely on this. Drop the dead attribute and add a panic() after it to make this expectation explicit. Calling `wfi` in the powerdown sequence is terminal so even if the function was made to return, there would be no functional change. This is useful for a following patch that makes psci_power_down_wfi() return. Change-Id: I62ca1ee058b1eaeb046966c795081e01bf45a2eb Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
336 lines
9.3 KiB
C
336 lines
9.3 KiB
C
/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTK_PM_H
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#define MTK_PM_H
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#include <lib/psci/psci.h>
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#if MTK_PUBEVENT_ENABLE
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#include <vendor_pubsub_events.h>
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#endif
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#define MTK_CPUPM_E_OK 0
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#define MTK_CPUPM_E_UNKNOWN -1
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#define MTK_CPUPM_E_ERR -2
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#define MTK_CPUPM_E_FAIL -3
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#define MTK_CPUPM_E_NOT_SUPPORT -4
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#define MTK_CPUPM_FN_PWR_LOCK_AQUIRE BIT(0)
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#define MTK_CPUPM_FN_INIT BIT(1)
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#define MTK_CPUPM_FN_PWR_STATE_VALID BIT(2)
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#define MTK_CPUPM_FN_PWR_ON_CORE_PREPARE BIT(3)
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#define MTK_CPUPM_FN_SUSPEND_CORE BIT(4)
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#define MTK_CPUPM_FN_RESUME_CORE BIT(5)
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#define MTK_CPUPM_FN_SUSPEND_CLUSTER BIT(6)
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#define MTK_CPUPM_FN_RESUME_CLUSTER BIT(7)
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#define MTK_CPUPM_FN_SUSPEND_MCUSYS BIT(8)
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#define MTK_CPUPM_FN_RESUME_MCUSYS BIT(9)
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#define MTK_CPUPM_FN_CPUPM_GET_PWR_STATE BIT(10)
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#define MTK_CPUPM_FN_SMP_INIT BIT(11)
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#define MTK_CPUPM_FN_SMP_CORE_ON BIT(12)
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#define MTK_CPUPM_FN_SMP_CORE_OFF BIT(13)
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#define MTK_CPUPM_FN_PWR_DOMAIN_POWER_DOWN_WFI BIT(14)
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enum mtk_cpupm_pstate {
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MTK_CPUPM_CORE_ON,
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MTK_CPUPM_CORE_OFF,
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MTK_CPUPM_CORE_SUSPEND,
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MTK_CPUPM_CORE_RESUME,
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MTK_CPUPM_CLUSTER_SUSPEND,
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MTK_CPUPM_CLUSTER_RESUME,
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MTK_CPUPM_MCUSYS_SUSPEND,
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MTK_CPUPM_MCUSYS_RESUME,
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};
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enum mtk_cpu_pm_mode {
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MTK_CPU_PM_CPUIDLE,
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MTK_CPU_PM_SMP,
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};
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#define MT_IRQ_REMAIN_MAX 32
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#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
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struct mt_irqremain {
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unsigned int count;
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unsigned int irqs[MT_IRQ_REMAIN_MAX];
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unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX];
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unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX];
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};
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typedef void (*plat_init_func)(unsigned int, uintptr_t);
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struct plat_pm_smp_ctrl {
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plat_init_func init;
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int (*pwr_domain_on)(u_register_t mpidr);
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void (*pwr_domain_off)(const psci_power_state_t *target_state);
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void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
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};
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struct plat_pm_pwr_ctrl {
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void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
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void (*pwr_domain_on_finish_late)(
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const psci_power_state_t *target_state);
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void (*pwr_domain_suspend_finish)(
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const psci_power_state_t *target_state);
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int (*validate_power_state)(unsigned int power_state,
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psci_power_state_t *req_state);
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void (*get_sys_suspend_power_state)(
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psci_power_state_t *req_state);
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void (*pwr_domain_pwr_down_wfi)(
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const psci_power_state_t *req_state);
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};
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struct plat_pm_reset_ctrl {
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__dead2 void (*system_off)();
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__dead2 void (*system_reset)();
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int (*system_reset2)(int is_vendor,
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int reset_type,
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u_register_t cookie);
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};
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struct mtk_cpu_pm_info {
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unsigned int cpuid;
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unsigned int mode;
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};
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struct mtk_cpu_pm_state {
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unsigned int afflv;
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unsigned int state_id;
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const psci_power_state_t *raw;
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};
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struct mtk_cpupm_pwrstate {
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struct mtk_cpu_pm_info info;
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struct mtk_cpu_pm_state pwr;
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};
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struct mtk_cpu_smp_ops {
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void (*init)(unsigned int cpu, uintptr_t sec_entrypoint);
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int (*cpu_pwr_on_prepare)(unsigned int cpu, uintptr_t entry);
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void (*cpu_on)(const struct mtk_cpupm_pwrstate *state);
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void (*cpu_off)(const struct mtk_cpupm_pwrstate *state);
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int (*invoke)(unsigned int funcID, void *priv);
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};
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#define CPUPM_PWR_REQ_UID_MAGIC 0x1103BAAD
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#ifdef CPU_PM_PWR_REQ_DEBUG
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#define DECLARE_CPUPM_PWR_REQ(var_name)\
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static struct cpupm_pwr_req var_name = {\
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.stat.name = #var_name,\
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.stat.uid = CPUPM_PWR_REQ_UID_MAGIC,\
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.stat.sta_req = 0,\
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}
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#else
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#define DECLARE_CPUPM_PWR_REQ(name)\
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static struct cpupm_pwr_req name = {\
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.stat.uid = CPUPM_PWR_REQ_UID_MAGIC,\
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.stat.sta_req = 0,\
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}
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#endif
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#define CPUPM_PWR_REQ_ACTIVE(_cpupm_req) ({\
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int in_ret;\
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in_ret = plat_pm_invoke_func(MTK_CPU_PM_CPUIDLE,\
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CPUPM_INVOKE_PWR_REQ_ACTIVE,\
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&_cpupm_req);\
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in_ret; })
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#define CPUPM_PWR_REQ_ACQUIRE(_cpupm_req, _pm_req) ({\
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int in_ret;\
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_cpupm_req.req = _pm_req;\
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in_ret = plat_pm_invoke_func(MTK_CPU_PM_CPUIDLE,\
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CPUPM_INVOKE_PWR_REQ_ACQUIRE,\
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&_cpupm_req);\
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in_ret; })
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#define CPUPM_PWR_REQ_RELEASE(_cpupm_req, _pm_req) ({\
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int in_ret;\
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_cpupm_req.req = _pm_req;\
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in_ret = plat_pm_invoke_func(MTK_CPU_PM_CPUIDLE,\
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CPUPM_INVOKE_PWR_REQ_RELASE,\
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&_cpupm_req);\
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in_ret; })
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struct cpupm_pwr_stat_req {
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unsigned int sta_req;
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unsigned int uid;
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#ifdef CPU_PM_PWR_REQ_DEBUG
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const char *name;
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#endif
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};
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struct cpupm_pwr_req {
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unsigned int req;
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struct cpupm_pwr_stat_req stat;
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};
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struct cpupm_invoke_data {
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union {
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unsigned int v_u32;
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struct cpupm_pwr_req *req;
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} val;
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};
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enum cpupm_invoke_func_id {
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/* Get regular active cpumask */
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CPUPM_INVOKE_WAKED_CPU = 0,
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CPUPM_INVOKE_PWR_REQ_ACTIVE,
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CPUPM_INVOKE_PWR_REQ_ACQUIRE,
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CPUPM_INVOKE_PWR_REQ_RELASE,
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};
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#define MT_CPUPM_MCUSYS_REQ (MT_CPUPM_PWR_DOMAIN_MCUSYS | \
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MT_CPUPM_PWR_DOMAIN_MCUSYS_BY_CLUSTER)
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#define MT_CPUPM_PWR_DOMAIN_CORE BIT(0)
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#define MT_CPUPM_PWR_DOMAIN_PERCORE_DSU BIT(1)
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#define MT_CPUPM_PWR_DOMAIN_PERCORE_DSU_MEM BIT(2)
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#define MT_CPUPM_PWR_DOMAIN_CLUSTER BIT(3)
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#define MT_CPUPM_PWR_DOMAIN_MCUSYS BIT(4)
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#define MT_CPUPM_PWR_DOMAIN_SUSPEND BIT(5)
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#define MT_CPUPM_PWR_DOMAIN_MCUSYS_BY_CLUSTER BIT(6)
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enum mt_cpupm_pwr_domain {
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CPUPM_PWR_ON,
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CPUPM_PWR_OFF,
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};
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#define mtk_pstate_type unsigned int
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struct mtk_cpu_pm_ops {
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void (*init)(unsigned int cpu, uintptr_t sec_entrypoint);
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unsigned int (*get_pstate)(enum mt_cpupm_pwr_domain domain,
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const mtk_pstate_type psci_state,
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const struct mtk_cpupm_pwrstate *state);
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int (*pwr_state_valid)(unsigned int afflv, unsigned int state);
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void (*cpu_suspend)(const struct mtk_cpupm_pwrstate *state);
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void (*cpu_resume)(const struct mtk_cpupm_pwrstate *state);
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void (*cluster_suspend)(const struct mtk_cpupm_pwrstate *state);
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void (*cluster_resume)(const struct mtk_cpupm_pwrstate *state);
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void (*mcusys_suspend)(const struct mtk_cpupm_pwrstate *state);
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void (*mcusys_resume)(const struct mtk_cpupm_pwrstate *state);
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int (*pwr_domain_pwr_down_wfi)(unsigned int cpu);
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int (*invoke)(unsigned int funcID, void *priv);
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};
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int register_cpu_pm_ops(unsigned int fn_flags, struct mtk_cpu_pm_ops *ops);
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int register_cpu_smp_ops(unsigned int fn_flags, struct mtk_cpu_smp_ops *ops);
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struct mt_cpupm_event_data {
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unsigned int cpuid;
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unsigned int pwr_domain;
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};
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/* Extension event for platform driver */
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#if MTK_PUBEVENT_ENABLE
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/* [PUB_EVENT] Core power on */
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#define MT_CPUPM_SUBCRIBE_EVENT_PWR_ON(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_pwr_on, _fn)
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/* [PUB_EVENT] Core power off */
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#define MT_CPUPM_SUBCRIBE_EVENT_PWR_OFF(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_pwr_off, _fn)
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/* [PUB_EVENT] Cluster power on */
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#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_on, _fn)
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/* [PUB_EVENT] Cluster power off */
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#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_OFF(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_off, _fn)
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/* [PUB_EVENT] Mcusys power on */
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#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_ON(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_on, _fn)
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/* [PUB_EVENT] Mcusys power off */
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#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_OFF(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_off, _fn)
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/* [PUB_EVENT] el3 time sync */
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#define MT_CPUPM_SUBCRIBE_EL3_UPTIME_SYNC_WITH_KERNEL(_fn) \
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SUBSCRIBE_TO_EVENT(el3_uptime_sync_with_kernel, _fn)
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#else
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#define MT_CPUPM_SUBCRIBE_EVENT_PWR_ON(_fn)
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#define MT_CPUPM_SUBCRIBE_EVENT_PWR_OFF(_fn)
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#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(_fn)
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#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_OFF(_fn)
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#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_ON(_fn)
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#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_OFF(_fn)
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#define MT_CPUPM_SUBCRIBE_EL3_UPTIME_SYNC_WITH_KERNEL(_fn)
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#endif
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/*
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* Definition c-state power domain.
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* bit 0: Cluster
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* bit 1: CPU buck
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* bit 2: Mcusys
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* bit 3: Memory
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* bit 4: System pll
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* bit 5: System bus
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* bit 6: SoC 26m/DCXO
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* bit 7: Vcore buck
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* bit 8~14: Reserved
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* bit 15: Suspend
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*/
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#define MT_PLAT_PWR_STATE_CLUSTER 0x0001
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#define MT_PLAT_PWR_STATE_MCUSYS 0x0005
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#define MT_PLAT_PWR_STATE_MCUSYS_BUCK 0x0007
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#define MT_PLAT_PWR_STATE_SYSTEM_MEM 0x000F
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#define MT_PLAT_PWR_STATE_SYSTEM_PLL 0x001F
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#define MT_PLAT_PWR_STATE_SYSTEM_BUS 0x007F
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#define MT_PLAT_PWR_STATE_SYSTEM_VCORE 0x00FF
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#define MT_PLAT_PWR_STATE_SUSPEND 0x80FF
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#define IS_MT_PLAT_PWR_STATE(_state, _tar) \
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(((_state) & _tar) == _tar)
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#define IS_MT_PLAT_PWR_STATE_MCUSYS(state) \
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IS_MT_PLAT_PWR_STATE(state, MT_PLAT_PWR_STATE_MCUSYS)
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#define IS_MT_PLAT_PWR_STATE_SYSTEM(state) ((state) & 0x7ff8)
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#ifdef PLAT_AFFLV_SYSTEM
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#define PLAT_MT_SYSTEM_SUSPEND PLAT_AFFLV_SYSTEM
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#else
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#define PLAT_MT_SYSTEM_SUSPEND PLAT_MAX_OFF_STATE
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#endif
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#ifdef PLAT_AFFLV_CLUSTER
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#define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_AFFLV_CLUSTER
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#else
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#define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE
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#endif
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#ifdef PLAT_AFFLV_MCUSYS
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#define PLAT_MT_CPU_SUSPEND_MCUSYS PLAT_AFFLV_MCUSYS
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#else
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#define PLAT_MT_CPU_SUSPEND_MCUSYS PLAT_MAX_RET_STATE
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#endif
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#define IS_PLAT_SYSTEM_SUSPEND(aff) ((aff) == PLAT_MT_SYSTEM_SUSPEND)
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#define IS_PLAT_SYSTEM_RETENTION(aff) ((aff) >= PLAT_MAX_RET_STATE)
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#define IS_PLAT_SUSPEND_ID(stateid) \
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((stateid) == MT_PLAT_PWR_STATE_SUSPEND)
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#define IS_PLAT_MCUSYSOFF_AFFLV(_afflv) \
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((_afflv) >= PLAT_MT_CPU_SUSPEND_MCUSYS)
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int plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl *ops);
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int plat_pm_ops_setup_reset(struct plat_pm_reset_ctrl *ops);
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int plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl *ops);
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uintptr_t plat_pm_get_warm_entry(void);
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int plat_pm_invoke_func(enum mtk_cpu_pm_mode mode, unsigned int id, void *priv);
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#endif
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