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https://github.com/ARM-software/arm-trusted-firmware.git
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29d1e29d7c
Support FDT for Agilex5 platform 1. Created wrapper file socfpga_dt.c 2. Added in Agilex5 dts file 3. Implemented fdt_check_header 4. Implemented gic configuration 5. Implemented dram configuration Remove init of FDT as Agilex5 has no plan to roll out FDT at the moment. Change-Id: If3990ed9524c6da5b3cb8966b63bc4a95d01fcda Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
127 lines
3.5 KiB
C
127 lines
3.5 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv3.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <tools_share/firmware_image_package.h>
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#include "socfpga_dt.h"
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static const void *fdt;
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/*******************************************************************************
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* This function checks device tree file with its header.
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* Returns 0 on success and a negative FDT error code on failure.
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******************************************************************************/
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int socfpga_dt_open_and_check(uintptr_t dt_addr, char *compatible_str)
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{
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int ret = 0;
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int node = 1;
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ret = fdt_check_header((void *)dt_addr);
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if (ret != 0) {
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ERROR("SOCFPGA: FDT Header invalid\n");
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return ret;
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}
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fdt = (const void *)dt_addr;
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/* As libfdt use void *, we can't avoid this cast */
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const void *dtb = (void *)dt_addr;
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/* Assert the node offset point to compatible property */
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node = fdt_node_offset_by_compatible(dtb, -1, compatible_str);
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if (node < 0) {
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ERROR("SOCFPGA: Can't find `%s` compatible in dtb\n",
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compatible_str);
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return node;
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}
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NOTICE("SOCFPGA: Successfully open and check FDT\n");
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return ret;
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}
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int socfpga_dt_populate_gicv3_config(uintptr_t dt_addr, gicv3_driver_data_t *plat_driver_data)
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{
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int err;
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int node;
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uintptr_t addr;
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)dt_addr;
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/*
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* Find the offset of the node containing "arm,gic-v3" compatible property.
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* Populating fconf strucutures dynamically is not supported for legacy
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* systems which use GICv2 IP. Simply skip extracting GIC properties.
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*/
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node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
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if (node < 0) {
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ERROR("SOCFPGA: Unable to locate node with arm,gic-v3 compatible property\n");
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return 0;
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}
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/* The GICv3 DT binding holds at least two address/size pairs,
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* the first describing the distributor, the second the redistributors.
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* See: bindings/interrupt-controller/arm,gic-v3.yaml
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*/
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err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
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if (err < 0) {
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ERROR("SOCFPGA: Failed to read GICD reg property of GIC node\n");
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} else {
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plat_driver_data->gicd_base = addr;
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}
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err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
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if (err < 0) {
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ERROR("SOCFPGA: Failed to read GICR reg property of GIC node\n");
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} else {
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plat_driver_data->gicr_base = addr;
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}
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return err;
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}
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int socfpga_dt_populate_dram_layout(uintptr_t dt_addr)
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{
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int node;
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uintptr_t addr;
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size_t size;
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)dt_addr;
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/* Find 'memory' node */
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node = fdt_node_offset_by_prop_value(hw_config_dtb, -1, "device_type",
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"memory", sizeof("memory"));
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if (node < 0) {
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NOTICE("SOCFPGA: Unable to locate 'memory' node\n");
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return node;
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}
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int err = fdt_get_reg_props_by_index(
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hw_config_dtb, node, 0,
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&addr, (size_t *)&size);
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NOTICE("SOCFPGA: Mem base 0x%lx, Mem size 0x%lx\n", addr, size);
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if (err < 0) {
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ERROR("SOCFPGA: Failed to read 'reg' property of 'memory' node\n");
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return err;
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}
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return 0;
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}
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