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3e318e4037
During cold boot, the initial translation tables are created with data
caches disabled, so all modifications go to memory directly. After the
MMU is enabled and data cache is enabled, any modification to the tables
goes to data cache, and eventually may get flushed to memory.
If CPU0 modifies the tables while CPU1 is off, CPU0 will have the
modified tables in its data cache. When CPU1 is powered on, the MMU is
enabled, then it enables coherency, and then it enables the data cache.
Until this is done, CPU1 isn't in coherency, and the translation tables
it sees can be outdated if CPU0 still has some modified entries in its
data cache.
This can be a problem in some cases. For example, the warm boot code
uses only the tables mapped during cold boot, which don't normally
change. However, if they are modified (and a RO page is made RW, or a XN
page is made executable) the CPU will see the old attributes and crash
when it tries to access it.
This doesn't happen in systems with HW_ASSISTED_COHERENCY or
WARMBOOT_ENABLE_DCACHE_EARLY. In these systems, the data cache is
enabled at the same time as the MMU. As soon as this happens, the CPU is
in coherency.
There was an attempt of a fix in psci_helpers.S, but it didn't solve the
problem. That code has been deleted. The code was introduced in commit
<264410306381> ("Invalidate TLB entries during warm boot").
Now, during a map or unmap operation, the memory associated to each
modified table is flushed. Traversing a table will also flush it's
memory, as there is no way to tell in the current implementation if the
table that has been traversed has also been modified.
Change-Id: I4b520bca27502f1018878061bc5fb82af740bb92
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
148 lines
4.3 KiB
ArmAsm
148 lines
4.3 KiB
ArmAsm
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <psci.h>
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.globl psci_do_pwrdown_cache_maintenance
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.globl psci_do_pwrup_cache_maintenance
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.globl psci_power_down_wfi
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/* -----------------------------------------------------------------------
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* void psci_do_pwrdown_cache_maintenance(unsigned int power level);
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*
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* This function performs cache maintenance for the specified power
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* level. The levels of cache affected are determined by the power
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* level which is passed as the argument i.e. level 0 results
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* in a flush of the L1 cache. Both the L1 and L2 caches are flushed
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* for a higher power level.
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*
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* Additionally, this function also ensures that stack memory is correctly
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* flushed out to avoid coherency issues due to a change in its memory
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* attributes after the data cache is disabled.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrdown_cache_maintenance
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push {r4, lr}
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/* ----------------------------------------------
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* Turn OFF cache and do stack maintenance
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* prior to cpu operations . This sequence is
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* different from AArch64 because in AArch32 the
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* assembler routines for cpu operations utilize
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* the stack whereas in AArch64 it doesn't.
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* ----------------------------------------------
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*/
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mov r4, r0
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bl do_stack_maintenance
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/* ---------------------------------------------
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* Invoke CPU-specifc power down operations for
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* the appropriate level
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* ---------------------------------------------
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*/
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mov r0, r4
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pop {r4, lr}
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b prepare_cpu_pwr_dwn
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endfunc psci_do_pwrdown_cache_maintenance
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/* -----------------------------------------------------------------------
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* void psci_do_pwrup_cache_maintenance(void);
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*
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* This function performs cache maintenance after this cpu is powered up.
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* Currently, this involves managing the used stack memory before turning
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* on the data cache.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrup_cache_maintenance
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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/* ---------------------------------------------
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* Ensure any inflight stack writes have made it
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* to main memory.
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* ---------------------------------------------
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*/
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dmb st
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in r1. Calculate and store the
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* stack base address in r0.
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* ---------------------------------------------
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*/
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bl plat_get_my_stack
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mov r1, sp
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sub r1, r0, r1
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mov r0, sp
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bl inv_dcache_range
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/* ---------------------------------------------
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* Enable the data cache.
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* ---------------------------------------------
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*/
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ldcopr r0, SCTLR
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orr r0, r0, #SCTLR_C_BIT
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stcopr r0, SCTLR
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isb
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pop {r12, pc}
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endfunc psci_do_pwrup_cache_maintenance
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/* ---------------------------------------------
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* void do_stack_maintenance(void)
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* Do stack maintenance by flushing the used
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* stack to the main memory and invalidating the
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* remainder.
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* ---------------------------------------------
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*/
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func do_stack_maintenance
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push {r4, lr}
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bl plat_get_my_stack
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/* Turn off the D-cache */
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ldcopr r1, SCTLR
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bic r1, #SCTLR_C_BIT
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stcopr r1, SCTLR
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isb
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in r1.
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* ---------------------------------------------
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*/
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mov r4, r0
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mov r1, sp
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sub r1, r0, r1
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mov r0, sp
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bl flush_dcache_range
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/* ---------------------------------------------
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* Calculate and store the size of the unused
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* stack memory in r1. Calculate and store the
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* stack base address in r0.
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* ---------------------------------------------
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*/
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sub r0, r4, #PLATFORM_STACK_SIZE
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sub r1, sp, r0
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bl inv_dcache_range
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pop {r4, pc}
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endfunc do_stack_maintenance
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/* -----------------------------------------------------------------------
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* This function is called to indicate to the power controller that it
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* is safe to power down this cpu. It should not exit the wfi and will
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* be released from reset upon power up.
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* -----------------------------------------------------------------------
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*/
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func psci_power_down_wfi
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dsb sy // ensure write buffer empty
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wfi
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no_ret plat_panic_handler
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endfunc psci_power_down_wfi
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