mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
29332bcd68
Add required code to support FCONF on STM32MP1 platform. The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2. It will be used to configure the addresses where to load other binaries. BL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min), so optee_utils.c is always compiled, and some OP-TEE flags are removed. Change-Id: Id957b49b0117864136250bfc416664f815043ada Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
470 lines
16 KiB
C
470 lines
16 KiB
C
/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_DEF_H
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#define STM32MP1_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/st/stm32mp1_rcc.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#ifndef __ASSEMBLER__
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#include <drivers/st/bsec.h>
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#include <drivers/st/stm32mp1_clk.h>
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#include <boot_api.h>
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#include <stm32mp_auth.h>
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#include <stm32mp_common.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_shres_helpers.h>
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#include <stm32mp1_dbgmcu.h>
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#include <stm32mp1_private.h>
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#include <stm32mp1_shared_resources.h>
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#endif
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#if !STM32MP_USE_STM32IMAGE
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#include "stm32mp1_fip_def.h"
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#else /* STM32MP_USE_STM32IMAGE */
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#include "stm32mp1_stm32image_def.h"
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#endif /* STM32MP_USE_STM32IMAGE */
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/*******************************************************************************
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* CHIP ID
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******************************************************************************/
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#define STM32MP1_CHIP_ID U(0x500)
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#define STM32MP157C_PART_NB U(0x05000000)
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#define STM32MP157A_PART_NB U(0x05000001)
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#define STM32MP153C_PART_NB U(0x05000024)
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#define STM32MP153A_PART_NB U(0x05000025)
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#define STM32MP151C_PART_NB U(0x0500002E)
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#define STM32MP151A_PART_NB U(0x0500002F)
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#define STM32MP157F_PART_NB U(0x05000080)
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#define STM32MP157D_PART_NB U(0x05000081)
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#define STM32MP153F_PART_NB U(0x050000A4)
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#define STM32MP153D_PART_NB U(0x050000A5)
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#define STM32MP151F_PART_NB U(0x050000AE)
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#define STM32MP151D_PART_NB U(0x050000AF)
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#define STM32MP1_REV_B U(0x2000)
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#define STM32MP1_REV_Z U(0x2001)
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/*******************************************************************************
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* PACKAGE ID
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******************************************************************************/
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#define PKG_AA_LFBGA448 U(4)
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#define PKG_AB_LFBGA354 U(3)
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#define PKG_AC_TFBGA361 U(2)
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#define PKG_AD_TFBGA257 U(1)
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/*******************************************************************************
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* STM32MP1 memory map related constants
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******************************************************************************/
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#define STM32MP_ROM_BASE U(0x00000000)
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#define STM32MP_ROM_SIZE U(0x00020000)
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#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
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#define STM32MP_SYSRAM_SIZE U(0x00040000)
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#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
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#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
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STM32MP_SYSRAM_SIZE - \
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STM32MP_NS_SYSRAM_SIZE)
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#define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
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#define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
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#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
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#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
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STM32MP_NS_SYSRAM_SIZE)
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/* DDR configuration */
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#define STM32MP_DDR_BASE U(0xC0000000)
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#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
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/* DDR power initializations */
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#ifndef __ASSEMBLER__
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enum ddr_type {
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STM32MP_DDR3,
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STM32MP_LPDDR2,
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STM32MP_LPDDR3
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};
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#endif
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/* Section used inside TF binaries */
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#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
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/* 256 Octets reserved for header */
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#define STM32MP_HEADER_SIZE U(0x00000100)
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#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE)
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#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
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(STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE))
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/* BL2 and BL32/sp_min require 4 tables */
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#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
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*/
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#if defined(IMAGE_BL2)
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#define MAX_MMAP_REGIONS 11
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#endif
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#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
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#define STM32MP_BL33_MAX_SIZE U(0x400000)
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/* Define maximum page size for NAND devices */
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#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
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/*******************************************************************************
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* STM32MP1 device/io map related constants (used for MMU)
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******************************************************************************/
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#define STM32MP1_DEVICE1_BASE U(0x40000000)
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#define STM32MP1_DEVICE1_SIZE U(0x40000000)
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#define STM32MP1_DEVICE2_BASE U(0x80000000)
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#define STM32MP1_DEVICE2_SIZE U(0x40000000)
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/*******************************************************************************
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* STM32MP1 RCC
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******************************************************************************/
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#define RCC_BASE U(0x50000000)
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/*******************************************************************************
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* STM32MP1 PWR
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******************************************************************************/
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#define PWR_BASE U(0x50001000)
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/*******************************************************************************
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* STM32MP1 GPIO
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******************************************************************************/
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#define GPIOA_BASE U(0x50002000)
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#define GPIOB_BASE U(0x50003000)
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#define GPIOC_BASE U(0x50004000)
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#define GPIOD_BASE U(0x50005000)
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#define GPIOE_BASE U(0x50006000)
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#define GPIOF_BASE U(0x50007000)
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#define GPIOG_BASE U(0x50008000)
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#define GPIOH_BASE U(0x50009000)
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#define GPIOI_BASE U(0x5000A000)
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#define GPIOJ_BASE U(0x5000B000)
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#define GPIOK_BASE U(0x5000C000)
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#define GPIOZ_BASE U(0x54004000)
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#define GPIO_BANK_OFFSET U(0x1000)
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/* Bank IDs used in GPIO driver API */
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#define GPIO_BANK_A U(0)
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#define GPIO_BANK_B U(1)
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#define GPIO_BANK_C U(2)
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#define GPIO_BANK_D U(3)
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#define GPIO_BANK_E U(4)
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#define GPIO_BANK_F U(5)
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#define GPIO_BANK_G U(6)
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#define GPIO_BANK_H U(7)
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#define GPIO_BANK_I U(8)
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#define GPIO_BANK_J U(9)
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#define GPIO_BANK_K U(10)
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#define GPIO_BANK_Z U(25)
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#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
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/*******************************************************************************
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* STM32MP1 UART
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******************************************************************************/
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#define USART1_BASE U(0x5C000000)
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#define USART2_BASE U(0x4000E000)
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#define USART3_BASE U(0x4000F000)
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#define UART4_BASE U(0x40010000)
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#define UART5_BASE U(0x40011000)
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#define USART6_BASE U(0x44003000)
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#define UART7_BASE U(0x40018000)
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#define UART8_BASE U(0x40019000)
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#define STM32MP_UART_BAUDRATE U(115200)
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/* For UART crash console */
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#define STM32MP_DEBUG_USART_BASE UART4_BASE
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/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
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#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
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#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
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#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
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#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
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#define DEBUG_UART_TX_GPIO_PORT 11
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#define DEBUG_UART_TX_GPIO_ALTERNATE 6
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#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
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#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
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#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
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#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
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/*******************************************************************************
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* STM32MP1 ETZPC
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******************************************************************************/
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#define STM32MP1_ETZPC_BASE U(0x5C007000)
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/* ETZPC TZMA IDs */
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#define STM32MP1_ETZPC_TZMA_ROM U(0)
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#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
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#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
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/* ETZPC DECPROT IDs */
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#define STM32MP1_ETZPC_STGENC_ID 0
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#define STM32MP1_ETZPC_BKPSRAM_ID 1
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#define STM32MP1_ETZPC_IWDG1_ID 2
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#define STM32MP1_ETZPC_USART1_ID 3
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#define STM32MP1_ETZPC_SPI6_ID 4
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#define STM32MP1_ETZPC_I2C4_ID 5
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#define STM32MP1_ETZPC_RNG1_ID 7
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#define STM32MP1_ETZPC_HASH1_ID 8
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#define STM32MP1_ETZPC_CRYP1_ID 9
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#define STM32MP1_ETZPC_DDRCTRL_ID 10
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#define STM32MP1_ETZPC_DDRPHYC_ID 11
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#define STM32MP1_ETZPC_I2C6_ID 12
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#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
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#define STM32MP1_ETZPC_TIM2_ID 16
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#define STM32MP1_ETZPC_TIM3_ID 17
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#define STM32MP1_ETZPC_TIM4_ID 18
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#define STM32MP1_ETZPC_TIM5_ID 19
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#define STM32MP1_ETZPC_TIM6_ID 20
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#define STM32MP1_ETZPC_TIM7_ID 21
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#define STM32MP1_ETZPC_TIM12_ID 22
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#define STM32MP1_ETZPC_TIM13_ID 23
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#define STM32MP1_ETZPC_TIM14_ID 24
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#define STM32MP1_ETZPC_LPTIM1_ID 25
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#define STM32MP1_ETZPC_WWDG1_ID 26
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#define STM32MP1_ETZPC_SPI2_ID 27
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#define STM32MP1_ETZPC_SPI3_ID 28
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#define STM32MP1_ETZPC_SPDIFRX_ID 29
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#define STM32MP1_ETZPC_USART2_ID 30
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#define STM32MP1_ETZPC_USART3_ID 31
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#define STM32MP1_ETZPC_UART4_ID 32
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#define STM32MP1_ETZPC_UART5_ID 33
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#define STM32MP1_ETZPC_I2C1_ID 34
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#define STM32MP1_ETZPC_I2C2_ID 35
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#define STM32MP1_ETZPC_I2C3_ID 36
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#define STM32MP1_ETZPC_I2C5_ID 37
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#define STM32MP1_ETZPC_CEC_ID 38
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#define STM32MP1_ETZPC_DAC_ID 39
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#define STM32MP1_ETZPC_UART7_ID 40
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#define STM32MP1_ETZPC_UART8_ID 41
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#define STM32MP1_ETZPC_MDIOS_ID 44
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#define STM32MP1_ETZPC_TIM1_ID 48
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#define STM32MP1_ETZPC_TIM8_ID 49
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#define STM32MP1_ETZPC_USART6_ID 51
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#define STM32MP1_ETZPC_SPI1_ID 52
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#define STM32MP1_ETZPC_SPI4_ID 53
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#define STM32MP1_ETZPC_TIM15_ID 54
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#define STM32MP1_ETZPC_TIM16_ID 55
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#define STM32MP1_ETZPC_TIM17_ID 56
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#define STM32MP1_ETZPC_SPI5_ID 57
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#define STM32MP1_ETZPC_SAI1_ID 58
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#define STM32MP1_ETZPC_SAI2_ID 59
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#define STM32MP1_ETZPC_SAI3_ID 60
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#define STM32MP1_ETZPC_DFSDM_ID 61
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#define STM32MP1_ETZPC_TT_FDCAN_ID 62
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#define STM32MP1_ETZPC_LPTIM2_ID 64
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#define STM32MP1_ETZPC_LPTIM3_ID 65
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#define STM32MP1_ETZPC_LPTIM4_ID 66
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#define STM32MP1_ETZPC_LPTIM5_ID 67
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#define STM32MP1_ETZPC_SAI4_ID 68
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#define STM32MP1_ETZPC_VREFBUF_ID 69
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#define STM32MP1_ETZPC_DCMI_ID 70
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#define STM32MP1_ETZPC_CRC2_ID 71
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#define STM32MP1_ETZPC_ADC_ID 72
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#define STM32MP1_ETZPC_HASH2_ID 73
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#define STM32MP1_ETZPC_RNG2_ID 74
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#define STM32MP1_ETZPC_CRYP2_ID 75
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#define STM32MP1_ETZPC_SRAM1_ID 80
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#define STM32MP1_ETZPC_SRAM2_ID 81
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#define STM32MP1_ETZPC_SRAM3_ID 82
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#define STM32MP1_ETZPC_SRAM4_ID 83
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#define STM32MP1_ETZPC_RETRAM_ID 84
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#define STM32MP1_ETZPC_OTG_ID 85
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#define STM32MP1_ETZPC_SDMMC3_ID 86
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#define STM32MP1_ETZPC_DLYBSD3_ID 87
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#define STM32MP1_ETZPC_DMA1_ID 88
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#define STM32MP1_ETZPC_DMA2_ID 89
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#define STM32MP1_ETZPC_DMAMUX_ID 90
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#define STM32MP1_ETZPC_FMC_ID 91
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#define STM32MP1_ETZPC_QSPI_ID 92
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#define STM32MP1_ETZPC_DLYBQ_ID 93
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#define STM32MP1_ETZPC_ETH_ID 94
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#define STM32MP1_ETZPC_RSV_ID 95
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#define STM32MP_ETZPC_MAX_ID 96
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/*******************************************************************************
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* STM32MP1 TZC (TZ400)
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******************************************************************************/
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#define STM32MP1_TZC_BASE U(0x5C006000)
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#define STM32MP1_TZC_A7_ID U(0)
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#define STM32MP1_TZC_M4_ID U(1)
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#define STM32MP1_TZC_LCD_ID U(3)
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#define STM32MP1_TZC_GPU_ID U(4)
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#define STM32MP1_TZC_MDMA_ID U(5)
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#define STM32MP1_TZC_DMA_ID U(6)
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#define STM32MP1_TZC_USB_HOST_ID U(7)
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#define STM32MP1_TZC_USB_OTG_ID U(8)
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#define STM32MP1_TZC_SDMMC_ID U(9)
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#define STM32MP1_TZC_ETH_ID U(10)
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#define STM32MP1_TZC_DAP_ID U(15)
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#define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
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TZC_400_REGION_ATTR_FILTER_BIT(1))
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/*******************************************************************************
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* STM32MP1 SDMMC
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******************************************************************************/
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#define STM32MP_SDMMC1_BASE U(0x58005000)
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#define STM32MP_SDMMC2_BASE U(0x58007000)
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#define STM32MP_SDMMC3_BASE U(0x48004000)
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#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
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#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
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#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
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#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
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#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
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/*******************************************************************************
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* STM32MP1 BSEC / OTP
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******************************************************************************/
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#define STM32MP1_OTP_MAX_ID 0x5FU
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#define STM32MP1_UPPER_OTP_START 0x20U
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#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
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/* OTP offsets */
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#define DATA0_OTP U(0)
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#define PART_NUMBER_OTP U(1)
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#define NAND_OTP U(9)
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#define PACKAGE_OTP U(16)
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#define HW2_OTP U(18)
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/* OTP mask */
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/* DATA0 */
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#define DATA0_OTP_SECURED BIT(6)
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/* PART NUMBER */
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#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
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#define PART_NUMBER_OTP_PART_SHIFT 0
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/* PACKAGE */
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#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
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#define PACKAGE_OTP_PKG_SHIFT 27
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/* IWDG OTP */
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#define HW2_OTP_IWDG_HW_POS U(3)
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#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
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#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
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/* HW2 OTP */
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#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
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/* NAND OTP */
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/* NAND parameter storage flag */
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#define NAND_PARAM_STORED_IN_OTP BIT(31)
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/* NAND page size in bytes */
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#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
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#define NAND_PAGE_SIZE_SHIFT 29
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#define NAND_PAGE_SIZE_2K U(0)
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#define NAND_PAGE_SIZE_4K U(1)
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#define NAND_PAGE_SIZE_8K U(2)
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/* NAND block size in pages */
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#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
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#define NAND_BLOCK_SIZE_SHIFT 27
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#define NAND_BLOCK_SIZE_64_PAGES U(0)
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#define NAND_BLOCK_SIZE_128_PAGES U(1)
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#define NAND_BLOCK_SIZE_256_PAGES U(2)
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/* NAND number of block (in unit of 256 blocs) */
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#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
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#define NAND_BLOCK_NB_SHIFT 19
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#define NAND_BLOCK_NB_UNIT U(256)
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/* NAND bus width in bits */
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#define NAND_WIDTH_MASK BIT(18)
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#define NAND_WIDTH_SHIFT 18
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/* NAND number of ECC bits per 512 bytes */
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#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
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#define NAND_ECC_BIT_NB_SHIFT 15
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#define NAND_ECC_BIT_NB_UNSET U(0)
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#define NAND_ECC_BIT_NB_1_BITS U(1)
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#define NAND_ECC_BIT_NB_4_BITS U(2)
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#define NAND_ECC_BIT_NB_8_BITS U(3)
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#define NAND_ECC_ON_DIE U(4)
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/* NAND number of planes */
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#define NAND_PLANE_BIT_NB_MASK BIT(14)
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/*******************************************************************************
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* STM32MP1 TAMP
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******************************************************************************/
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#define TAMP_BASE U(0x5C00A000)
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#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
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#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
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static inline uint32_t tamp_bkpr(uint32_t idx)
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{
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return TAMP_BKP_REGISTER_BASE + (idx << 2);
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}
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#endif
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/*******************************************************************************
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* STM32MP1 DDRCTRL
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******************************************************************************/
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#define DDRCTRL_BASE U(0x5A003000)
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/*******************************************************************************
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* STM32MP1 DDRPHYC
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******************************************************************************/
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#define DDRPHYC_BASE U(0x5A004000)
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/*******************************************************************************
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* STM32MP1 IWDG
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******************************************************************************/
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#define IWDG_MAX_INSTANCE U(2)
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#define IWDG1_INST U(0)
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#define IWDG2_INST U(1)
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|
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#define IWDG1_BASE U(0x5C003000)
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#define IWDG2_BASE U(0x5A002000)
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|
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/*******************************************************************************
|
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* Miscellaneous STM32MP1 peripherals base address
|
|
******************************************************************************/
|
|
#define BSEC_BASE U(0x5C005000)
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#define CRYP1_BASE U(0x54001000)
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#define DBGMCU_BASE U(0x50081000)
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#define HASH1_BASE U(0x54002000)
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#define I2C4_BASE U(0x5C002000)
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#define I2C6_BASE U(0x5c009000)
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#define RNG1_BASE U(0x54003000)
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#define RTC_BASE U(0x5c004000)
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|
#define SPI6_BASE U(0x5c001000)
|
|
#define STGEN_BASE U(0x5c008000)
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|
#define SYSCFG_BASE U(0x50020000)
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|
|
|
/*******************************************************************************
|
|
* Device Tree defines
|
|
******************************************************************************/
|
|
#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
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#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
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|
#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
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#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
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#endif /* STM32MP1_DEF_H */
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