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https://github.com/ARM-software/arm-trusted-firmware.git
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f7434fa135
The commitd76f012ea8("refactor(imx8m): replace magic number with enum type") also hardcodes the domain permissions configuration for the UARTs, causing a regression for any board using a boot console different from UART2. Indeed, previously, the RDC_PDAP_UARTn registers were set to the reset value (0xff), meaning all domains were enabled for read and write access. This patch fixes this regression by ensuring that the console always has read/write access enabled for domain 0. Tested on a i.MX8MN BSH SMM S2 PRO board. Fixes:d76f012ea8("refactor(imx8m): replace magic number with enum type") Change-Id: I2670bf485372f32ef45cebb72a7694a9a800f417 Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
73 lines
1.6 KiB
C
73 lines
1.6 KiB
C
/*
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* Copyright (c) 2019-2022 NXP. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX_RDC_H
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#define IMX_RDC_H
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#include <lib/utils_def.h>
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#include <imx_sec_def.h>
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#include <platform_def.h>
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#define MDAn(x) (IMX_RDC_BASE + 0x200 + (x) * 4)
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#define PDAPn(x) (IMX_RDC_BASE + 0x400 + (x) * 4)
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#define MRSAn(x) (IMX_RDC_BASE + 0x800 + (x) * 0x10)
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#define MREAn(x) (IMX_RDC_BASE + 0x804 + (x) * 0x10)
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#define MRCn(x) (IMX_RDC_BASE + 0x808 + (x) * 0x10)
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#define LCK BIT(31)
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#define SREQ BIT(30)
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#define ENA BIT(30)
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#define DID0 U(0x0)
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#define DID1 U(0x1)
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#define DID2 U(0x2)
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#define DID3 U(0x3)
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#define D3R BIT(7)
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#define D3W BIT(6)
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#define D2R BIT(5)
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#define D2W BIT(4)
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#define D1R BIT(3)
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#define D1W BIT(2)
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#define D0R BIT(1)
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#define D0W BIT(0)
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union rdc_setting {
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uint32_t rdc_mda; /* Master Domain Assignment */
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uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */
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uint32_t rdc_mem_region[3]; /* Memory Region Access Control */
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};
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enum rdc_type {
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RDC_INVALID,
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RDC_MDA,
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RDC_PDAP,
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RDC_MEM_REGION,
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};
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struct imx_rdc_cfg {
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enum rdc_type type; /* config type Master, Peripheral or Memory region */
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int index;
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union rdc_setting setting;
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};
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#define RDC_MDAn(i, mda) \
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{RDC_MDA, (i), .setting.rdc_mda = (mda), }
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#define RDC_PDAPn(i, pdap) \
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{RDC_PDAP, (i), .setting.rdc_pdap = (pdap), }
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#define RDC_MEM_REGIONn(i, msa, mea, mrc) \
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{ RDC_MEM_REGION, (i), \
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.setting.rdc_mem_region[0] = (msa), \
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.setting.rdc_mem_region[1] = (mea), \
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.setting.rdc_mem_region[2] = (mrc), \
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}
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void imx_rdc_init(struct imx_rdc_cfg *cfg, unsigned int console_base);
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#endif /* IMX_RDC_H */
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