mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
e365479d0d
TC4 adds a new SMMU-700 specifically for the DPU (in the RoS). This is used as the DPU SMMU instead of the existing SMMU used for both the GPU and DPU. Update the devicetree to reflect this. Note that the streamID values have also changes for this new SMMU. This is because TC4 also updates the new SMMU to use a different streamID for each DPU port - these must all be added to the device tree. Change-Id: If2ce9749e40937fd1291346d071b691cfb662f2e Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com>
67 lines
1.4 KiB
Text
67 lines
1.4 KiB
Text
/*
|
|
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <platform_def.h>
|
|
|
|
#define MHU_TX_ADDR 46240000 /* hex */
|
|
#define MHU_RX_ADDR 46250000 /* hex */
|
|
|
|
#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
|
|
#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
|
|
#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
|
|
|
|
#define ETHERNET_ADDR 64000000
|
|
#define ETHERNET_INT 799
|
|
|
|
#define SYS_REGS_ADDR 60080000
|
|
|
|
#define MMC_ADDR 600b0000
|
|
#define MMC_INT_0 778
|
|
#define MMC_INT_1 779
|
|
|
|
#define RTC_ADDR 600a0000
|
|
#define RTC_INT 777
|
|
|
|
#define KMI_0_ADDR 60100000
|
|
#define KMI_0_INT 784
|
|
#define KMI_1_ADDR 60110000
|
|
#define KMI_1_INT 785
|
|
|
|
#define VIRTIO_BLOCK_ADDR 60020000
|
|
#define VIRTIO_BLOCK_INT 769
|
|
|
|
#include "tc-common.dtsi"
|
|
#if TARGET_FLAVOUR_FVP
|
|
#include "tc-fvp.dtsi"
|
|
#else
|
|
#include "tc-fpga.dtsi"
|
|
#endif /* TARGET_FLAVOUR_FVP */
|
|
#include "tc3-4-base.dtsi"
|
|
|
|
/ {
|
|
smmu_700: iommu@3f000000 {
|
|
status = "okay";
|
|
};
|
|
|
|
smmu_700_dpu: iommu@4002a00000 {
|
|
status = "okay";
|
|
};
|
|
|
|
dp0: display@DPU_ADDR {
|
|
iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
|
|
<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
|
|
};
|
|
|
|
gpu: gpu@2d000000 {
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "IRQAW";
|
|
iommus = <&smmu_700 0x200>;
|
|
};
|
|
};
|