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e74d658181
Optimised the loop workaround for Spectre_BHB mitigation: 1. use of speculation barrier for cores implementing SB instruction. 2. use str/ldr instead of stp/ldp as the loop uses only X2 register. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I8ac53ea1e42407ad8004c1d59c05f791011f195d
30 lines
691 B
ArmAsm
30 lines
691 B
ArmAsm
/*
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* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <context.h>
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#if WORKAROUND_CVE_2022_23960
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/*
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* This macro applies the mitigation for CVE-2022-23960.
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* The macro saves x2 to the CPU context.
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* SP should point to the CPU context.
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*/
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.macro apply_cve_2022_23960_bhb_wa _bhb_loop_count
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str x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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/* CVE-BHB-NUM loop count */
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mov x2, \_bhb_loop_count
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1:
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/* b pc+4 part of the workaround */
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b 2f
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2:
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subs x2, x2, #1
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bne 1b
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speculation_barrier
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ldr x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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.endm
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#endif /* WORKAROUND_CVE_2022_23960 */
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