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https://github.com/ARM-software/arm-trusted-firmware.git
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9fc59639e6
This patch adds the functionality needed for platforms to provide Branch Target Identification (BTI) extension, introduced to AArch64 in Armv8.5-A by adding BTI instruction used to mark valid targets for indirect branches. The patch sets new GP bit [50] to the stage 1 Translation Table Block and Page entries to denote guarded EL3 code pages which will cause processor to trap instructions in protected pages trying to perform an indirect branch to any instruction other than BTI. BTI feature is selected by BRANCH_PROTECTION option which supersedes the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication and is disabled by default. Enabling BTI requires compiler support and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0. The assembly macros and helpers are modified to accommodate the BTI instruction. This is an experimental feature. Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3 is now made as an internal flag and BRANCH_PROTECTION flag should be used instead to enable Pointer Authentication. Note. USE_LIBROM=1 option is currently not supported. Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
99 lines
2.2 KiB
ArmAsm
99 lines
2.2 KiB
ArmAsm
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpuamu.h>
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.globl cpuamu_cnt_read
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.globl cpuamu_cnt_write
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.globl cpuamu_read_cpuamcntenset_el0
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.globl cpuamu_read_cpuamcntenclr_el0
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.globl cpuamu_write_cpuamcntenset_el0
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.globl cpuamu_write_cpuamcntenclr_el0
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/*
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* uint64_t cpuamu_cnt_read(unsigned int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `x0`.
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*/
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func cpuamu_cnt_read
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adr x1, 1f
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add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x1, x1, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x1
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1: read CPUAMEVCNTR0_EL0
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read CPUAMEVCNTR1_EL0
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read CPUAMEVCNTR2_EL0
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read CPUAMEVCNTR3_EL0
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read CPUAMEVCNTR4_EL0
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endfunc cpuamu_cnt_read
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/*
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* void cpuamu_cnt_write(unsigned int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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*/
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func cpuamu_cnt_write
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adr x2, 1f
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add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x2, x2, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x2
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1: write CPUAMEVCNTR0_EL0
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write CPUAMEVCNTR1_EL0
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write CPUAMEVCNTR2_EL0
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write CPUAMEVCNTR3_EL0
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write CPUAMEVCNTR4_EL0
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endfunc cpuamu_cnt_write
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/*
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* unsigned int cpuamu_read_cpuamcntenset_el0(void);
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*
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* Read the `CPUAMCNTENSET_EL0` CPU register and return
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* it in `x0`.
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*/
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func cpuamu_read_cpuamcntenset_el0
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mrs x0, CPUAMCNTENSET_EL0
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ret
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endfunc cpuamu_read_cpuamcntenset_el0
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/*
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* unsigned int cpuamu_read_cpuamcntenclr_el0(void);
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*
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* Read the `CPUAMCNTENCLR_EL0` CPU register and return
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* it in `x0`.
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*/
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func cpuamu_read_cpuamcntenclr_el0
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mrs x0, CPUAMCNTENCLR_EL0
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ret
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endfunc cpuamu_read_cpuamcntenclr_el0
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/*
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* void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
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*
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* Write `mask` to the `CPUAMCNTENSET_EL0` CPU register.
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*/
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func cpuamu_write_cpuamcntenset_el0
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msr CPUAMCNTENSET_EL0, x0
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ret
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endfunc cpuamu_write_cpuamcntenset_el0
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/*
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* void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
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*
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* Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register.
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*/
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func cpuamu_write_cpuamcntenclr_el0
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msr CPUAMCNTENCLR_EL0, x0
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ret
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endfunc cpuamu_write_cpuamcntenclr_el0
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