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https://github.com/ARM-software/arm-trusted-firmware.git
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2710bdadc4
Add the enablement mechanism for the MC_CGM dividers. The division factor is established by dividing the parent's rate by the rate of the divider's output. Change-Id: Iadb84f4f47531a67b0b1509b94e1f2b962631a77 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
137 lines
5.7 KiB
C
137 lines
5.7 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright 2020-2021, 2023-2025 NXP
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*/
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#ifndef S32CC_CLK_REGS_H
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#define S32CC_CLK_REGS_H
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#include <lib/utils_def.h>
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#define FXOSC_BASE_ADDR (0x40050000UL)
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#define ARMPLL_BASE_ADDR (0x40038000UL)
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#define PERIPHPLL_BASE_ADDR (0x4003C000UL)
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#define ARM_DFS_BASE_ADDR (0x40054000UL)
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#define PERIPH_DFS_BASE_ADDR (0x40058000UL)
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#define CGM0_BASE_ADDR (0x40030000UL)
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#define CGM1_BASE_ADDR (0x40034000UL)
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#define DDRPLL_BASE_ADDR (0x40044000UL)
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#define MC_ME_BASE_ADDR (0x40088000UL)
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#define MC_RGM_BASE_ADDR (0x40078000UL)
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#define RDC_BASE_ADDR (0x40080000UL)
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#define MC_CGM5_BASE_ADDR (0x40068000UL)
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/* FXOSC */
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#define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL)
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#define FXOSC_CTRL_OSC_BYP BIT_32(31U)
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#define FXOSC_CTRL_COMP_EN BIT_32(24U)
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#define FXOSC_CTRL_EOCV_OFFSET 16U
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#define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET)
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#define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \
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((uint32_t)(VAL) << FXOSC_CTRL_EOCV_OFFSET))
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#define FXOSC_CTRL_GM_SEL_OFFSET 4U
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#define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET)
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#define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \
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((uint32_t)(VAL) << FXOSC_CTRL_GM_SEL_OFFSET))
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#define FXOSC_CTRL_OSCON BIT_32(0U)
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#define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL)
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#define FXOSC_STAT_OSC_STAT BIT_32(31U)
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/* PLL */
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#define PLLDIG_PLLCR(PLL) ((PLL) + 0x0UL)
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#define PLLDIG_PLLCR_PLLPD BIT_32(31U)
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#define PLLDIG_PLLSR(PLL) ((PLL) + 0x4UL)
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#define PLLDIG_PLLSR_LOCK BIT_32(2U)
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#define PLLDIG_PLLDV(PLL) ((PLL) + 0x8UL)
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#define PLLDIG_PLLDV_RDIV_OFFSET 12U
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#define PLLDIG_PLLDV_RDIV_MASK GENMASK_32(14U, PLLDIG_PLLDV_RDIV_OFFSET)
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#define PLLDIG_PLLDV_RDIV_SET(VAL) (PLLDIG_PLLDV_RDIV_MASK & \
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((VAL) << PLLDIG_PLLDV_RDIV_OFFSET))
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#define PLLDIG_PLLDV_RDIV(VAL) (((VAL) & PLLDIG_PLLDV_RDIV_MASK) >> \
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PLLDIG_PLLDV_RDIV_OFFSET)
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#define PLLDIG_PLLDV_MFI_MASK GENMASK_32(7U, 0U)
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#define PLLDIG_PLLDV_MFI(DIV) (PLLDIG_PLLDV_MFI_MASK & (DIV))
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#define PLLDIG_PLLFD(PLL) ((PLL) + 0x10UL)
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#define PLLDIG_PLLFD_SMDEN BIT_32(30U)
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#define PLLDIG_PLLFD_MFN_MASK GENMASK_32(14U, 0U)
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#define PLLDIG_PLLFD_MFN_SET(VAL) (PLLDIG_PLLFD_MFN_MASK & (VAL))
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#define PLLDIG_PLLCLKMUX(PLL) ((PLL) + 0x20UL)
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#define PLLDIG_PLLODIV(PLL, N) ((PLL) + 0x80UL + ((N) * 0x4UL))
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#define PLLDIG_PLLODIV_DE BIT_32(31U)
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#define PLLDIG_PLLODIV_DIV_OFFSET 16U
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#define PLLDIG_PLLODIV_DIV_MASK GENMASK_32(23U, PLLDIG_PLLODIV_DIV_OFFSET)
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#define PLLDIG_PLLODIV_DIV(VAL) (((VAL) & PLLDIG_PLLODIV_DIV_MASK) >> \
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PLLDIG_PLLODIV_DIV_OFFSET)
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#define PLLDIG_PLLODIV_DIV_SET(VAL) (PLLDIG_PLLODIV_DIV_MASK & ((VAL) << \
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PLLDIG_PLLODIV_DIV_OFFSET))
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/* MMC_CGM */
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#define CGM_MUXn_CSC(CGM_ADDR, MUX) ((CGM_ADDR) + 0x300UL + ((MUX) * 0x40UL))
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#define MC_CGM_MUXn_CSC_SELCTL_OFFSET 24U
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#define MC_CGM_MUXn_CSC_SELCTL_MASK GENMASK_32(29U, MC_CGM_MUXn_CSC_SELCTL_OFFSET)
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#define MC_CGM_MUXn_CSC_SELCTL(val) (MC_CGM_MUXn_CSC_SELCTL_MASK & ((val) \
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<< MC_CGM_MUXn_CSC_SELCTL_OFFSET))
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#define MC_CGM_MUXn_CSC_CLK_SW BIT_32(2U)
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#define MC_CGM_MUXn_CSC_SAFE_SW BIT_32(3U)
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#define CGM_MUXn_CSS(CGM_ADDR, MUX) ((CGM_ADDR) + 0x304UL + ((MUX) * 0x40UL))
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#define MC_CGM_MUXn_CSS_SELSTAT_OFFSET 24U
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#define MC_CGM_MUXn_CSS_SELSTAT_MASK GENMASK_32(29U, MC_CGM_MUXn_CSS_SELSTAT_OFFSET)
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#define MC_CGM_MUXn_CSS_SELSTAT(css) ((MC_CGM_MUXn_CSS_SELSTAT_MASK & (css))\
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>> MC_CGM_MUXn_CSS_SELSTAT_OFFSET)
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#define MC_CGM_MUXn_CSS_SWTRG(css) ((MC_CGM_MUXn_CSS_SWTRG_MASK & (css)) \
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>> MC_CGM_MUXn_CSS_SWTRG_OFFSET)
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#define MC_CGM_MUXn_CSS_SWTRG_OFFSET 17U
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#define MC_CGM_MUXn_CSS_SWTRG_MASK GENMASK_32(19U, MC_CGM_MUXn_CSS_SWTRG_OFFSET)
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#define MC_CGM_MUXn_CSS_SWTRG_SUCCESS 0x1U
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#define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK 0x4U
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#define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE 0x5U
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#define MC_CGM_MUXn_CSS_SWIP BIT_32(16U)
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#define MC_CGM_MUXn_CSS_SAFE_SW BIT_32(3U)
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#define MC_CGM_MUXn_DCm(CGM_ADDR, MUX, DC) \
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(((CGM_ADDR) + 0x308UL) + \
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((MUX) * 0x40UL) + ((DC) * 0x4UL))
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#define MC_CGM_MUXn_DCm_DIV_OFFSET (16U)
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#define MC_CGM_MUXn_DCm_DIV_MASK GENMASK_32(23U, MC_CGM_MUXn_DCm_DIV_OFFSET)
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#define MC_CGM_MUXn_DCm_DIV_SET(VAL) (MC_CGM_MUXn_DCm_DIV_MASK & ((VAL) \
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<< MC_CGM_MUXn_DCm_DIV_OFFSET))
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#define MC_CGM_MUXn_DCm_DIV(VAL) ((MC_CGM_MUXn_DCm_DIV_MASK & (VAL)) \
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>> MC_CGM_MUXn_DCm_DIV_OFFSET)
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#define MC_CGM_MUXn_DCm_DE BIT_32(31U)
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#define MC_CGM_MUXn_DIV_UPD_STAT(CGM_ADDR, MUX) \
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(((CGM_ADDR) + 0x33CUL + ((MUX) * 0x40UL)))
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#define MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT_OFFSET (0U)
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#define MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT(CSS) \
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((MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT_MASK \
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& (CSS)) \
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>> MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT_OFFSET)
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#define MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT_MASK BIT_32(0U)
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/* DFS */
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#define DFS_PORTSR(DFS_ADDR) ((DFS_ADDR) + 0xCUL)
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#define DFS_PORTOLSR(DFS_ADDR) ((DFS_ADDR) + 0x10UL)
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#define DFS_PORTOLSR_LOL(N) (BIT_32(N) & GENMASK_32(5U, 0U))
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#define DFS_PORTRESET(DFS_ADDR) ((DFS_ADDR) + 0x14UL)
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#define DFS_PORTRESET_MASK GENMASK_32(5U, 0U)
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#define DFS_PORTRESET_SET(VAL) (((VAL) & DFS_PORTRESET_MASK))
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#define DFS_CTL(DFS_ADDR) ((DFS_ADDR) + 0x18UL)
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#define DFS_CTL_RESET BIT_32(1U)
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#define DFS_DVPORTn(DFS_ADDR, PORT) ((DFS_ADDR) + 0x1CUL + ((PORT) * 0x4UL))
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#define DFS_DVPORTn_MFI_MASK GENMASK_32(15U, 8U)
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#define DFS_DVPORTn_MFI_SHIFT 8U
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#define DFS_DVPORTn_MFN_MASK GENMASK_32(7U, 0U)
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#define DFS_DVPORTn_MFN_SHIFT 0U
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#define DFS_DVPORTn_MFI(MFI) (((MFI) & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_SHIFT)
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#define DFS_DVPORTn_MFN(MFN) (((MFN) & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_SHIFT)
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#define DFS_DVPORTn_MFI_SET(VAL) (((VAL) << DFS_DVPORTn_MFI_SHIFT) & DFS_DVPORTn_MFI_MASK)
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#define DFS_DVPORTn_MFN_SET(VAL) (((VAL) << DFS_DVPORTn_MFN_SHIFT) & DFS_DVPORTn_MFN_MASK)
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#endif /* S32CC_CLK_REGS_H */
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