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https://github.com/ARM-software/arm-trusted-firmware.git
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94a4383a2b
When RESET_TO_BL31 was enabled, CNTFRQ_EL0 was left uninitialized, leading to incorrect system counter frequency settings. This impacted timer-dependent components, such as SMMUv3, causing initialization failures and unpredictable behavior. To fix this, CNTFRQ_EL0 is now explicitly set using plat_get_syscnt_freq2(), ensuring the correct system timer frequency and proper initialization of dependent components. Signed-off-by: Lokesh B V <Lokesh.BV@Arm.com> Change-Id: I808b17d25c87c4dce1bc2c8171a800b69b5c2908
285 lines
7.9 KiB
C
285 lines
7.9 KiB
C
/*
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* Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <libfdt.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/css/css_mhu_doorbell.h>
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#include <drivers/arm/css/scmi.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_dyn_cfg_getter.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/css/common/css_pm.h>
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#include <plat/common/platform.h>
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#include <nrd_ras.h>
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#include <nrd_variant.h>
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nrd_platform_info_t nrd_plat_info;
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static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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};
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static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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},
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#if (NRD_CHIP_COUNT > 1)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(1),
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.db_reg_addr = PLAT_CSS_MHU_BASE
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+ NRD_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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},
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#endif
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#if (NRD_CHIP_COUNT > 2)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(2),
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.db_reg_addr = PLAT_CSS_MHU_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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},
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#endif
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#if (NRD_CHIP_COUNT > 3)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(3),
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.db_reg_addr = PLAT_CSS_MHU_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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},
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#endif
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};
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static scmi_channel_plat_info_t plat3_rd_scmi_info[] = {
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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},
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#if (NRD_CHIP_COUNT > 1)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(1),
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.db_reg_addr = PLAT_CSS_MHU_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(1) +
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MHU_V3_SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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},
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#endif
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#if (NRD_CHIP_COUNT > 2)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(2),
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.db_reg_addr = PLAT_CSS_MHU_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(2) +
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MHU_V3_SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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},
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#endif
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#if (NRD_CHIP_COUNT > 3)
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(3),
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.db_reg_addr = PLAT_CSS_MHU_BASE +
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NRD_REMOTE_CHIP_MEM_OFFSET(3) +
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MHU_V3_SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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},
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#endif
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};
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scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
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{
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if (nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
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nrd_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
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nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
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nrd_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
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nrd_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM ||
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nrd_plat_info.platform_id == RD_N2_CFG3_SID_VER_PART_NUM) {
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if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info)) {
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panic();
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}
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return &plat_rd_scmi_info[channel_id];
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} else if (nrd_plat_info.platform_id == RD_V3_SID_VER_PART_NUM ||
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nrd_plat_info.platform_id == RD_V3_CFG1_SID_VER_PART_NUM ||
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nrd_plat_info.platform_id == RD_V3_CFG2_SID_VER_PART_NUM) {
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if (channel_id >= ARRAY_SIZE(plat3_rd_scmi_info)) {
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panic();
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}
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return &plat3_rd_scmi_info[channel_id];
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} else if (nrd_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) {
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return &sgi575_scmi_plat_info;
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} else {
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panic();
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}
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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nrd_plat_info.platform_id = plat_arm_nrd_get_platform_id();
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nrd_plat_info.config_id = plat_arm_nrd_get_config_id();
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nrd_plat_info.multi_chip_mode = plat_arm_nrd_get_multi_chip_mode();
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#if RESET_TO_BL31
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#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
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/* Set the counter frequency for the generic timer */
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write_cntfrq_el0(plat_get_syscnt_freq2());
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#endif
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#endif /* RESET_TO_BL31 */
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/* Initialize generic timer */
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generic_delay_timer_init();
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#if SPMD_SPM_AT_SEL2 && !RESET_TO_BL31
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INFO("BL31 FCONF: FW_CONFIG address = 0x%lx\n", (uintptr_t)arg1);
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/* Initialize BL31's copy of the DTB registry because SPMD needs the
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* TOS_FW_CONFIG's addresses to make a copy.
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*/
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fconf_populate("FW_CONFIG", arg1);
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/* arg1 is supposed to point to SOC_FW_CONFIG */
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const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
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soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID);
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if (soc_fw_config_info != NULL) {
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arg1 = soc_fw_config_info->config_addr;
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}
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#endif /* SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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}
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/*******************************************************************************
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* This function inserts platform information via device tree nodes as,
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* system-id {
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* platform-id = <0>;
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* config-id = <0>;
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* }
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******************************************************************************/
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#if RESET_TO_BL31
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static int append_config_node(uintptr_t fdt_base_addr, uintptr_t fdt_base_size)
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{
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void *fdt;
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int nodeoffset, err;
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unsigned int platid = 0, platcfg = 0;
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if (fdt_base_addr == 0) {
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ERROR("NT_FW CONFIG base address is NULL\n");
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return -1;
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}
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fdt = (void *)fdt_base_addr;
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/* Check the validity of the fdt */
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if (fdt_check_header(fdt) != 0) {
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ERROR("Invalid NT_FW_CONFIG DTB passed\n");
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return -1;
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}
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nodeoffset = fdt_subnode_offset(fdt, 0, "system-id");
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if (nodeoffset < 0) {
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ERROR("Failed to get system-id node offset\n");
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return -1;
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}
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platid = plat_arm_nrd_get_platform_id();
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err = fdt_setprop_u32(fdt, nodeoffset, "platform-id", platid);
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if (err < 0) {
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ERROR("Failed to set platform-id\n");
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return -1;
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}
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platcfg = plat_arm_nrd_get_config_id();
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err = fdt_setprop_u32(fdt, nodeoffset, "config-id", platcfg);
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if (err < 0) {
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ERROR("Failed to set config-id\n");
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return -1;
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}
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platcfg = plat_arm_nrd_get_multi_chip_mode();
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err = fdt_setprop_u32(fdt, nodeoffset, "multi-chip-mode", platcfg);
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if (err < 0) {
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ERROR("Failed to set multi-chip-mode\n");
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return -1;
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}
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flush_dcache_range((uintptr_t)fdt, fdt_base_size);
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return 0;
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}
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#endif
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void nrd_bl31_common_platform_setup(void)
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{
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arm_bl31_platform_setup();
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/* Configure the warm reboot SGI for primary core */
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css_setup_cpu_pwr_down_intr();
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#if CSS_SYSTEM_GRACEFUL_RESET
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/* Register priority level handlers for reboot */
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ehf_register_priority_handler(PLAT_REBOOT_PRI,
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css_reboot_interrupt_handler);
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#endif
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#if RESET_TO_BL31
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int ret = append_config_node(NRD_CSS_BL31_PRELOAD_DTB_BASE,
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NRD_CSS_BL31_PRELOAD_DTB_SIZE);
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if (ret != 0) {
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panic();
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}
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#endif
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}
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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{
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/*
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* For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are
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* supported.
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*/
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if (((nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
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(nrd_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) {
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ops->cpu_standby = NULL;
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ops->system_off = NULL;
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ops->system_reset = NULL;
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ops->get_sys_suspend_power_state = NULL;
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ops->pwr_domain_suspend = NULL;
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ops->pwr_domain_suspend_finish = NULL;
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}
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return css_scmi_override_pm_ops(ops);
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}
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