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26cf5cf6d6
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by CubeMX. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional "st,phy-cal" After this patch the built-in calibration is always executed. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
158 lines
3 KiB
C
158 lines
3 KiB
C
/*
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* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#ifndef STM32MP1_DDR_H
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#define STM32MP1_DDR_H
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#include <stdbool.h>
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#include <stdint.h>
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#define DT_DDR_COMPAT "st,stm32mp1-ddr"
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struct stm32mp1_ddr_size {
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uint64_t base;
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uint64_t size;
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};
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/**
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* struct ddr_info
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*
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* @dev: pointer for the device
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* @info: UCLASS RAM information
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* @ctl: DDR controleur base address
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* @phy: DDR PHY base address
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* @syscfg: syscfg base address
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*/
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struct ddr_info {
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struct stm32mp1_ddr_size info;
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struct stm32mp1_ddrctl *ctl;
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struct stm32mp1_ddrphy *phy;
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uintptr_t pwr;
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uintptr_t rcc;
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};
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struct stm32mp1_ddrctrl_reg {
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uint32_t mstr;
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uint32_t mrctrl0;
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uint32_t mrctrl1;
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uint32_t derateen;
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uint32_t derateint;
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uint32_t pwrctl;
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uint32_t pwrtmg;
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uint32_t hwlpctl;
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uint32_t rfshctl0;
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uint32_t rfshctl3;
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uint32_t crcparctl0;
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uint32_t zqctl0;
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uint32_t dfitmg0;
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uint32_t dfitmg1;
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uint32_t dfilpcfg0;
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uint32_t dfiupd0;
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uint32_t dfiupd1;
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uint32_t dfiupd2;
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uint32_t dfiphymstr;
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uint32_t odtmap;
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uint32_t dbg0;
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uint32_t dbg1;
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uint32_t dbgcmd;
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uint32_t poisoncfg;
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uint32_t pccfg;
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};
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struct stm32mp1_ddrctrl_timing {
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uint32_t rfshtmg;
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uint32_t dramtmg0;
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uint32_t dramtmg1;
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uint32_t dramtmg2;
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uint32_t dramtmg3;
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uint32_t dramtmg4;
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uint32_t dramtmg5;
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uint32_t dramtmg6;
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uint32_t dramtmg7;
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uint32_t dramtmg8;
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uint32_t dramtmg14;
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uint32_t odtcfg;
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};
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struct stm32mp1_ddrctrl_map {
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uint32_t addrmap1;
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uint32_t addrmap2;
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uint32_t addrmap3;
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uint32_t addrmap4;
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uint32_t addrmap5;
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uint32_t addrmap6;
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uint32_t addrmap9;
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uint32_t addrmap10;
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uint32_t addrmap11;
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};
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struct stm32mp1_ddrctrl_perf {
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uint32_t sched;
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uint32_t sched1;
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uint32_t perfhpr1;
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uint32_t perflpr1;
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uint32_t perfwr1;
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uint32_t pcfgr_0;
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uint32_t pcfgw_0;
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uint32_t pcfgqos0_0;
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uint32_t pcfgqos1_0;
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uint32_t pcfgwqos0_0;
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uint32_t pcfgwqos1_0;
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uint32_t pcfgr_1;
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uint32_t pcfgw_1;
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uint32_t pcfgqos0_1;
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uint32_t pcfgqos1_1;
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uint32_t pcfgwqos0_1;
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uint32_t pcfgwqos1_1;
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};
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struct stm32mp1_ddrphy_reg {
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uint32_t pgcr;
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uint32_t aciocr;
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uint32_t dxccr;
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uint32_t dsgcr;
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uint32_t dcr;
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uint32_t odtcr;
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uint32_t zq0cr1;
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uint32_t dx0gcr;
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uint32_t dx1gcr;
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uint32_t dx2gcr;
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uint32_t dx3gcr;
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};
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struct stm32mp1_ddrphy_timing {
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uint32_t ptr0;
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uint32_t ptr1;
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uint32_t ptr2;
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uint32_t dtpr0;
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uint32_t dtpr1;
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uint32_t dtpr2;
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uint32_t mr0;
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uint32_t mr1;
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uint32_t mr2;
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uint32_t mr3;
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};
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struct stm32mp1_ddr_info {
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const char *name;
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uint32_t speed; /* in kHZ */
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uint32_t size; /* Memory size in byte = col * row * width */
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};
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struct stm32mp1_ddr_config {
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struct stm32mp1_ddr_info info;
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struct stm32mp1_ddrctrl_reg c_reg;
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struct stm32mp1_ddrctrl_timing c_timing;
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struct stm32mp1_ddrctrl_map c_map;
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struct stm32mp1_ddrctrl_perf c_perf;
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struct stm32mp1_ddrphy_reg p_reg;
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struct stm32mp1_ddrphy_timing p_timing;
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};
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int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed);
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void stm32mp1_ddr_init(struct ddr_info *priv,
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struct stm32mp1_ddr_config *config);
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#endif /* STM32MP1_DDR_H */
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