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940ecd072c
Add basic CPU library code to support the Alto CPU. Change-Id: I45958be99c4a350a32a9e511d3705fb568b97236 Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>
66 lines
1.8 KiB
ArmAsm
66 lines
1.8 KiB
ArmAsm
/*
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* Copyright (c) 2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_alto.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Alto must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Alto supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_func_start cortex_alto
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_alto
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func cortex_alto_core_pwr_dwn
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#if ENABLE_SME_FOR_NS
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/* ---------------------------------------------------
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* Disable SME if enabled and supported
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* ---------------------------------------------------
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*/
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mrs x0, ID_AA64PFR1_EL1
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ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
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#ID_AA64PFR1_EL1_SME_WIDTH
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cmp x0, #SME_NOT_IMPLEMENTED
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b.eq 1f
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msr CORTEX_ALTO_SVCRSM, xzr
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msr CORTEX_ALTO_SVCRZA, xzr
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1:
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#endif
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_ALTO_IMP_CPUPWRCTLR_EL1, \
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CORTEX_ALTO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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isb
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ret
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endfunc cortex_alto_core_pwr_dwn
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.section .rodata.cortex_alto_regs, "aS"
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cortex_alto_regs: /* The ASCII list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_alto_cpu_reg_dump
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adr x6, cortex_alto_regs
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mrs x8, CORTEX_ALTO_IMP_CPUECTLR_EL1
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ret
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endfunc cortex_alto_cpu_reg_dump
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declare_cpu_ops cortex_alto, CORTEX_ALTO_MIDR, \
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cortex_alto_reset_func, \
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cortex_alto_core_pwr_dwn
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