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The new Allwinner H616 SoC lacks the management controller and the secure SRAM A2, so we need to tweak the memory map quite substantially: We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our compressed virtual address space (max 256MB) anymore, so we revert to the full 32bit VA space and use a flat mapping throughout all of it. The missing controller also means we need to always use the native PSCI ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC. Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
99 lines
3.5 KiB
ReStructuredText
99 lines
3.5 KiB
ReStructuredText
Allwinner ARMv8 SoCs
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====================
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Allwinner
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SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
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PSCI runtime services.
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Building TF-A
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-------------
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To build for machines with an A64 or H5 SoC:
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.. code:: shell
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
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To build for machines with an H6 SoC:
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.. code:: shell
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
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To build for machines with an H616 or H313 SoC:
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.. code:: shell
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h616 DEBUG=1 bl31
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Installation
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------------
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U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot).
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Loading is done from SD card, eMMC or SPI flash, also via an USB debug
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interface (FEL).
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After building bl31.bin, the binary must be fed to the U-Boot build system
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to include it in the FIT image that the SPL loader will process.
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bl31.bin can be either copied (or sym-linked) into U-Boot's root directory,
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or the environment variable BL31 must contain the binary's path.
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See the respective `U-Boot documentation`_ for more details.
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.. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64
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Memory layout
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-------------
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A64, H5 and H6 SoCs
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~~~~~~~~~~~~~~~~~~~
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BL31 lives in SRAM A2, which is documented to be accessible from secure
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world only. Since this SRAM region is very limited (48 KB), we take
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several measures to reduce memory consumption. One of them is to confine
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BL31 to only 28 bits of virtual address space, which reduces the number
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of required page tables (each occupying 4KB of memory).
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The mapping we use on those SoCs is as follows:
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::
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0 64K 16M 1GB 1G+160M physical address
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+-+------+-+---+------+--...---+-------+----+------+----------
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|B| |S|///| |//...///| |////| |
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|R| SRAM |C|///| dev |//...///| (sec) |////| BL33 | DRAM ...
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|O| |P|///| MMIO |//...///| DRAM |////| |
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|M| | |///| |//...///| (32M) |////| |
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+-+------+-+---+------+--...---+-------+----+------+----------
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| | | | | | / / / /
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| | | | | | / / / /
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| | | | | | / / / /
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| | | | | | / // /
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| | | | | | / / /
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+-+------+-+---+------+--+-------+------+
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|B| |S|///| |//| | |
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|R| SRAM |C|///| dev |//| sec | BL33 |
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|O| |P|///| MMIO |//| DRAM | |
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|M| | |///| |//| | |
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+-+------+-+---+------+--+-------+------+
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0 64K 16M 160M 192M 256M virtual address
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H616 SoC
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~~~~~~~~
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The H616 lacks the secure SRAM region present on the other SoCs, also
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lacks the "ARISC" management processor (SCP) we use. BL31 thus needs to
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run from DRAM, which prevents our compressed virtual memory map described
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above. Since running in DRAM also lifts the restriction of the limited
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SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
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address space. So the virtual addresses used in BL31 match the physical
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addresses as presented above.
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Trusted OS dispatcher
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---------------------
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One can boot Trusted OS(OP-TEE OS, bl32 image) along side bl31 image on Allwinner A64.
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In order to include the 'opteed' dispatcher in the image, pass 'SPD=opteed' on the command line
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while compiling the bl31 image and make sure the loader (SPL) loads the Trusted OS binary to
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the beginning of DRAM (0x40000000).
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